View PEX8114-BC13BIG_5949289.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 january, 2007 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book version 3.0 january 2007 website www.plxtech.com technical support www.plxtech.com/support phone 800 759-3735 408 774-9060 fax 408 774-2169
copyright information copyright ? 2006 ? 2007 plx technology, inc. all rights reserved. the information in this document is proprietary to plx technology. no part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from plx technology. plx technology provides this documentation withou t warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. while the information contained herein is believed to be accurate, such information is pr eliminary, and no representations or warranties of accuracy or completeness are made. in no event will plx technology be liable for damages arising directly or indirectly from any us e of or reliance upon the informati on contained in this document. plx technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. plx technology retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx technology products. plx technology and the plx logo are registered tr ademarks and expresslane is a trademark of plx technology, inc. pci express is a trademark of the pci special interest group (pci-sig). all product names are trademarks, re gistered trademarks, or servicem arks of their respective owners. order number: 8114bc-sil-db-p1-3.0 data book plx technology, inc. ii expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0
january, 2007 revision history expresslane pex 8114bc pci express-to-pci/pci-x bridge data book iii copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 revision history version date description of changes 1.0 june, 2006 initial production re lease, silicon revision ba. 1.1 august, 2006 added notes regardi ng nt mode errata. revised register 17-12, offset 30h expansion rom base address . updated miscellaneous elec trical specifications. added pull-up information for jt ag_tck, and removed pull-up information from ee_pr# and all hot plug outputs. moved thermal resistance informat ion to chapter 20 (from chapter 19) and added heat sink -related information. miscellaneous corrections throughout the data book. 2.0 december, 2006 production release, silicon revision bb. removed support for silicon revisi on ba and non-transparent mode. miscellaneous corrections and e nhancements thr oughout data book. 3.0 january, 2007 production release, silicon revision bc.
data book plx technology, inc. iv expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 preface the information contained in this document is subject to change without notice. this document is periodically updated as new information is made available. audience this data book provides the functional details of the plx expresslane pex 8114bc pci express-to- pci/pci-x bridge, for hardware designe rs and software/firmware engineers. supplemental documentation this data book assumes that the reader is familiar with the following documents: ? plx technology, inc. 870 w maude avenue, sunnyvale, ca 94085 usa tel: 800 759-3735 (domestic only) 408 774-9060, fax: 408 774-2169, www.plxtech.com ? pex 8114b c design checklist application note ? pex 8114bc errata the plx pex 8114 toolbox includes other pex 8114 documentation as well. pci special interest group (pci-sig) 3855 sw 153rd drive, beaverton, or 97006 usa tel: 503 619-0569, fax: 503 644-6708, www.pcisig.com ? pci local bus specification, revision 2.3 ? pci local bus specification, revision 3.0 ? pci express card electromechanical (cem) specification, revision 1.0a ? pci express card electromechanical (cem) specification, revision 1.1 ? pci to pci bridge architecture specification, revision 1.1 ? pci bus power management interface specification, revision 1.2 ? pci hot plug specification, revision 1.1 ? pci standard hot plug controller and subsystem specification, revision 1.0 ? pci-x addendum to pci local bus specification, revision 1.0b ? pci-x addendum to pci local bus specification, revision 2.0a ? pci express base specification, revision 1.0a ? pci express to pci/pci-x bridge specification, revision 1.0 ? pci-x electrical and mechanical addendum to the pci local bus specification, revision 2.0a the institute of electrical a nd electronics engineers, inc. 445 hoes lane, piscataway, nj 08854-4141 usa tel: 800 701-4333 (domestic only) or 732 981-0060, fax: 732 981-9667, www.ieee.org ? ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture, 1990 ? ieee standard 1149.1a-1993, ieee standard test access port and boundary-scan architecture ? ieee standard 1149.1b-1994, specifications for ven dor-specific extensions ? ieee standard 1149.6-2003, ieee standard test access port and boundary-scan architecture extensions
january, 2007 supplemental documentation abbreviations expresslane pex 8114bc pci express-to-pci/pci-x bridge data book v copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 supplemental document ation abbreviations in this data book, shortened titles are provided to the previously listed documents. the following table defines these abbreviations. data assignment conventions abbreviation document pci r3.0 pci local bus specification, revision 3.0 pci expresscard cem r1.0a pci express card electromec hanical (cem) specification, revision 1.0a pci expresscard cem r1.1 pci express card electromec hanical (cem) specification, revision 1.1 pci-to-pci bridge r1.1 pci to pci bridge architecture specification, revision 1.1 pci power mgmt. r1.2 pci bus power management interface specificat ion, revision 1.2 pci hot plug r1.1 pci hot plug specification, revision 1.1 pci standard hot plug controller and subsystem r1.0 pci standard hot plug controll er and subsystem specification, revision 1.0 pci-x r1.0b pci-x addendum to pci lo cal bus specification, revision 1.0b pci-x r2.0a pci-x addendum to pci lo cal bus specification, revision 2.0a pci express r1.0a pci express ba se specification, revision 1.0a pci express-to-pci/pci-x bridge r1.0 pci express to pci/pci-x bridge specification, revision 1.0 ieee standard 1149.1-1990 ieee st andard test access port and boundary-scan architecture ieee standard 1149.6-2003 ieee standard test access port and boundary-scan architecture extensions data width pex 8114 convention 1 byte (8 bits) byte 2 bytes (16 bits) word 4 bytes (32 bits) dword/dword
data book plx technology, inc. vi expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 terms and abbreviations the following table defines common terms and abbr eviations used in this document. terms and abbreviations defined in the pci express r1.0a are not included in this table. terms and abbreviations definition # active-low signal. ack acknowledge control packet. a cont rol packet used by a destinati on to acknowledge data packet receipt. a signal that acknowledges signal receipt. adb allowable disconnect boundary. adq allowable disconnect quantity. in the pci express in terface, the adq is a buff er size, which is used to indicate memory requirements or reserves. bar base address register. bcr bridge control register of the type 1 csr space. bridge, transparent provides connectivity from the conventional pci or pci-x bus system to the pci express hierarchy or subsystem. the bridge not only converts the physical bus to pci express point-to-point signaling, it also translates the pci or pc i-x bus protocol to pci express protocol. the transparent bridge allows the address domain on one side of the bri dge to be mapped into the cpu system hierarchy on the primary side of the bridge. cold reset a ?fundamental reset? following the applic ation of power. completer device addressed by a requester. cpl completion transaction. crc cyclic redundancy check csr configuration status register; control and st atus register; command and status register. dl_down data link layer is down (a pci express link/port status). dllp data link layer packet (origina te at the data link layer); al low flow control (fcx dllps) to acknowledge packet s (ack and nak dllps); and po wer management (pmx dllps). dw dword. ecc error checking and correction. eeprom electrically erasable programmable read-only memory. endpoint device, other than the root comp lex and switches that are request ers or completers of pci express transactions. endpoints can be pci express endpoin ts or conventional pci endpoints. conventional pci endpoints support i/o and lock ed transaction semantics. pci express endpoints do not. fcp flow control packet devices on each link exchange fcps, which carry header and data payload credit information for one of three packet type s ? posted requests, n on-posted requests, and completions. fundamental reset the mechanism of setting or returning all registers and state machines to default/initial conditions, as defined in all pci express, pci, pci-x and bri dge specifications. this mechanism is implemented by way of the pex_perst# input ball/signal. host a host computer provides services to computers that connect to it on a network. it is considered in charge over the remainder of devices connected on the bus. hot reset a reset propagated in-ba nd across a link using a physical la yer mechanism (training sequence).
january, 2007 terms and abbreviations expresslane pex 8114bc pci express-to-pci/pci-x bridge data book vii copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 i cmos input. i/o cmos bi-direc tional input/output. inch ingress credit handler. itch internal credit handler. lane differential signal pair in each direction. layers pci express defines three layers: transaction layer ? provides assembly and disassembly of tlps, the major components of which are header, data payload, and an optional digest field. data link layer ? provides link management and data inte grity, including error detection and correction. defines the data control for pci express. physical layer ? appears to the upper layers as pci . connects the lower protocols to the upper layers. link physical connection between two devices that consists of x n lanes . a x1 link consists of 1 transmit and 1 receive si gnal, where each signal is a differential pair. this is one lane. there are four lines or signals in a x1 link. a x4 link contains four lanes or f our differential signal pairs for each direction, for a total of 16 lines or signals. llist link list. lvdsrn differential low-voltage, high-spe ed, lvds negative receiver inputs. lvdsrp differential low-voltage, high-s peed, lvds positive receiver inputs. lvdstn differential low-voltage, high-speed, lvds negative transmitter outputs. lvdstp differential low-voltage, high-speed, lvds positive transmitter outputs. terms and abbreviations definition a differential pair a differential pair in each direction = one lane this is an x1 link there are four signals this is an x4 link there are 16 signals a differential pair in each direction and four of them = four lanes
data book plx technology, inc. viii expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 mam master abort mode. msi message signaled interrupt. mwi memory write and invalidate. nak negative acknowledge. non-posted request packet packet transmitted by a requester that has a completion packet returned by the associated completer. npr non-posted request. ns no snoop. o cmos output. od open drain output. packet types there are three packet types: tlp , transaction layer packet dllp , data link layer packet plp , physical layer packet pci peripheral component inte rconnect. a pci bus is a high-perfo rmance, 32- or 64-bit bus. it is designed to use with devices that contain high-bandwidth requirements; for example , the display subsystem. a pci bus is an i/o bu s that can be dynami cally configured. pci pci/pci-x compliant. pci-x peripheral component inte rconnect. an extension to pci, de signed to address the need for the increased bandwidth of pci devices. pex pci express. port interface between a pci express component and the li nk, and consists of transmitters and receivers. an ingress port receives a packet. an egress port that transmits a packet. posted request packet packet transmitted by a requester that does have a completion packet returned by the associated completer. pr posted request. pu signal is internally pulled up. qos quality of service. rc root complex. device that c onnects the cpu and memory subsys tem to the pci express fabric, which supports one or more pci express ports. rcb read completion boundary. requester device that originates a tr ansaction or places a transaction sequence into the pci express fabric. ro relaxed ordering. rohs restrictions on the use of certain hazardous substances (rohs) directive. rx receiver. sops station operations block. terms and abbreviations definition
january, 2007 terms and abbreviations expresslane pex 8114bc pci express-to-pci/pci-x bridge data book ix copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 sticky bits status bits that are reset to default on a fundamental reset. st icky bits are not modified or initialized by a reset, except a fundamental reset. devices th at consume aux power preserve register values when aux power consumptio n is enabled (by way of aux power or pme enable). hwinit, ros, r/ws. and r/w1cs csr types. (refer to table 14-2 for csr type definitions.) strap strapping pads must be tied hi gh to vdd33 or low to vss on the board. sts pci-x sustained three- state output, driven high for one clk before float. switch device that appears to software as two or more logical pci-to-pci bridges. tc traffic class. tlp translation layer packet. tp totem pole. ts three-state bi-directional. tx transceiver. vc virtual channel. warm reset ?fundamenta l reset? without cycl ing the supplied power. terms and abbreviations definition
data book plx technology, inc. x expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 data book notations and conventions notation / convention description blue text indicates that the text is hyperlinked to its description elsewhere in the data book. left-click the blue text to learn more about the hyperlinked information. this format is often used for register names, register bit and field names, register offsets, chapter and section titles, figures, and tables. pex_xxxp[3:0] when the signal name appears in all caps, with the primary port description listed first, fi eld [3:0] indicates the num ber of signal balls/pads assigned to that port. the lowercase ?p = positive? or ?n = negative? suffix indicates the differential pair of si gnal, which are always used together. # = active-low signals unless specified otherwise, active-low signals are identified by a ?#? appended to the term ( for example , pex_perst#). program/code samples monospace font ( program or code samples ) is used to identify code samples or programming references. these code samples are case-sensitive, unless specified otherwise. command_done interrupt format. command/status register names. parity error detected register parameter [field] or control function. upper base address[31:16] specific function in 32-bit register bounded by bits [31:16]. number multipliers k = 1,000 (10 3 ) is generally used with frequency response. k = 1,024 (2 10 ) is used for memory size references. kb = 1,024 bytes. m = meg. = 1,000,000 when referring to frequency (decimal notation) = 1,048,576 when referring to me mory sizes (binary notation) 1fh h = suffix which identifies hex values. each prefix term is equivalent to a 4-bit binary value (nibble). legal prefix terms are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f. 1010b b = suffix which identifies binary notation ( for example , 01b, 010b, 1010b, and so forth). not used with single-digit values of 0 or 1. 0 through 9 decimal numbers, or single binary numbers. byte eight bits ? abbreviated to ?b? ( for example , 4b = 4 bytes) lsb least-significant byte. lsb least-significant bit. msb most-significant byte. msb most-significant bit. dword dword (32 bits) is the primar y register size in these devices. reserved do not modify reserved bits and words. unless specified otherwise, these bits read as 0 and must be written as 0.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book xi copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 contents chapter 1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pex 8114 serial pci express to pci/pci-x bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.1 introduction to pex 8114 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1 physical layer ? layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 data link layer ? layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.3 transaction layer ? layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.4 sample paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.4.1 forward transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.4.2 reverse transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 pex 8114 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.1 pci express adapter board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.2 pci express motherboard to pci-x expansion slot . . . . . . . . . . . . . . . . . . . . . 10 1.4.3 pci-x host supporting a pci express expansion slot . . . . . . . . . . . . . . . . . . . 11 1.4.4 pci-x add-in boar d created from pci express native silicon . . . . . . . . . . . . . 12 1.4.5 pci-x extender board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 2 signal ball description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 2.2 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 pci/pci-x bus interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 pci express interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 hot plug signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.6 strapping signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7 jtag interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 serial eeprom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.9 power and ground signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.10 ball assignments by location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.11 ball assignments by signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.12 physical ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 chapter 3 clock and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1 pex 8114 clocking introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.1 pci-x clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.2 pci-x clocking of pci-x module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.2.1 clocking the pci module when pex 8114 clock generator is not used . 46 3.1.2.2 clocking the pci module when pex 8114 clock generator is used . . . . . 46 3.2 determining pci bus and internal clock initialization . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.1 determining bus mode ca pability and maximum frequency . . . . . . . . . . . . . . 48 3.3 pci clock master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.1 clock master mode signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4 pci clock slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.1 clock slave ? forward transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . 52 3.4.2 clock slave ? reverse transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . 54 3.4.3 timing diagrams ? forward or reverse transparent bridge mode . . . . . . . . . 55
contents plx technology, inc. xii expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.1 level-0, fundamental reset (power-on, hard, cold, warm) . . . . . . . . . . . . . . 58 3.5.1.1 pex_perst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.5.1.2 level-0 reset ? forward transparent bridge mode . . . . . . . . . . . . . . . . . 59 3.5.1.3 level-0 reset ? reverse transparent bridge mode . . . . . . . . . . . . . . . . . 60 3.5.2 level-1, hot reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5.2.1 level-1 reset ? forward transparent bridge mode . . . . . . . . . . . . . . . . . 61 3.5.2.2 level-1 reset ? reverse transparent bridge mode . . . . . . . . . . . . . . . . . 62 3.5.3 secondary bus reset, level-2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.5.3.1 level-2 reset ? forward transparent bridge mode . . . . . . . . . . . . . . . . . 63 3.5.3.2 level-2 reset ? reverse transparent bridge mode . . . . . . . . . . . . . . . . . 63 3.6 serial eeprom load sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 chapter 4 data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.1 internal data path description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 pci express credits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3 latency and bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.1 data flow-through latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.2 pci transaction initial latency and cycle recovery time . . . . . . . . . . . . . . . . 66 4.3.3 pci-x transaction initial latency and cycle recovery time . . . . . . . . . . . . . . 67 4.3.4 arbitration latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 5 address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2 supported address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2.1 i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.2.1.1 enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.2.1.2 i/o base and limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.2.1.3 isa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.2.1.4 vga mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2.2 memory-mapped i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2.2.1 enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2.2.2 memory-mapped i/o base and limit registers . . . . . . . . . . . . . . . . . . . . . 75 5.2.3 prefetchable space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.3.1 enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.3.2 prefetchable base and limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2.3.3 64-bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.4 base address register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 chapter 6 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2 type 0 configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3 type 1 configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.4 type 1-to-type 0 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.1 forward transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.2 reverse transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 type 1-to-type 1 forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5.1 forward transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5.2 reverse transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.6 pci express enhanced configuration mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.7 configuration retry mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.7.1 forward transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.7.2 reverse transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
january, 2007 plx technology, inc. expresslane pex 8114bc pci express-to-pci/pci-x bridge data book xiii copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.8 configuration methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.8.1 configuration methods intent and variations . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.8.2 pci express extended configuration method . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.8.3 pci configuration cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.8.4 bar0/1 device-specific register memory-mapped configuration . . . . . . . . . . 90 6.8.5 address and data pointer configuration method . . . . . . . . . . . . . . . . . . . . . . . 91 6.8.6 configuration specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.8.6.1 forward transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.8.6.2 reverse transparent bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 chapter 7 bridge operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 7.2 general compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 pci-to-pci express transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.1 pci-to-pci express flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.2 pci-to-pci express ? pci posted write requests . . . . . . . . . . . . . . . . . . . . . . 96 7.3.3 pci-to-pci express ? pci non-posted requests . . . . . . . . . . . . . . . . . . . . . . . 97 7.3.4 pci-to-pci express ? pci non-posted transactions until pci express completion returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3.5 pci-to-pci express ? pci requests do not contain predetermined lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3.5.1 memory read requests to non-prefetchable space . . . . . . . . . . . . . . . . 98 7.3.5.2 memory read requests to prefetchable space . . . . . . . . . . . . . . . . . . . . 98 7.3.5.3 memory read line or memory read line multiple . . . . . . . . . . . . . . . . . . 99 7.3.5.4 credits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.3.6 pci-to-pci express disposition of unused prefetched data . . . . . . . . . . . . . . 99 7.3.7 pci-to-pci express pending transaction count limits . . . . . . . . . . . . . . . . . 100 7.3.8 pci-to-pci express ? pci write transaction with discontiguous byte enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.3.9 pci-to-pci express ? pci write transactions larger than maximum packet size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.4 pci-x-to-pci express transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.4.1 pci-x-to-pci express flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.4.2 pci-x-to-pci express ? pci-x posted requests . . . . . . . . . . . . . . . . . . . . . . 101 7.4.3 pci-x-to-pci express ? pci-x non-posted requests . . . . . . . . . . . . . . . . . . 102 7.4.4 pci-x-to-pci express ? pci-x read requests larger than maximum read request size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4.5 pci-x-to-pci express ? pci-x transfer special case . . . . . . . . . . . . . . . . . . 103 7.4.6 pci-x-to-pci express ? pci-x transactions that require bridge to take ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4.7 pci-x-to-pci express ? pci-x writes with discontiguous byte enables . . . . 104 7.4.8 pci-x-to-pci express ? pci-x writes longer than maximum packet size . . 104 7.5 pci express-to-pci transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.1 pci express-to-pci flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.2 pci express-to-pci ? pci express posted transactions . . . . . . . . . . . . . . . . 105 7.5.3 pci express-to-pci ? pci express non-posted transactions . . . . . . . . . . . . 106 7.5.4 pci express-to-pci ? pci bus retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.5.5 pci express-to-pci transaction request size . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5.6 pci express-to-pci transaction completion size . . . . . . . . . . . . . . . . . . . . . 107 7.6 pci express-to-pci-x transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.6.1 pci express-to-pci-x posted writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
contents plx technology, inc. xiv expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.6.2 pci express-to-pci-x non-posted transactions . . . . . . . . . . . . . . . . . . . . . . 109 7.6.2.1 non-posted writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.6.2.2 non-posted writes and reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.6.2.3 transaction concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.7 transaction transfer failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.7.1 pci endpoint fails to retry read request . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.7.2 pci-x endpoint fails to transmit split completion . . . . . . . . . . . . . . . . . . . . . 112 7.7.3 pci-x endpoint allows infinite retries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.7.4 pci express endpoint fails to return completion data . . . . . . . . . . . . . . . . . 113 chapter 8 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5 8.1 forward transparent bridge error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.1.1 forward transparent bridge pci express originating interface (primary to secondary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.1.1.1 received poisoned tlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.1.1.2 received ecrc error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.1.1.3 pci/pci-x uncorrectable data errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.1.1.4 pci/pci-x address/attribute errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.1.1.5 pci/pci-x master abort on posted transaction . . . . . . . . . . . . . . . . . . . 121 8.1.1.6 pci/pci-x master abort on non-posted transaction . . . . . . . . . . . . . . . . 121 8.1.1.7 pci-x master abort on split completion . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.1.1.8 pci/pci-x target abort on posted transaction . . . . . . . . . . . . . . . . . . . . 122 8.1.1.9 pci/pci-x target abort on non-posted transaction . . . . . . . . . . . . . . . . 123 8.1.1.10 pci-x target abort on split completion . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1.1.11 completer abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.1.1.12 unexpected completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.1.1.13 receive non-posted request unsupported . . . . . . . . . . . . . . . . . . . . . . 125 8.1.1.14 link training error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.1.1.15 data link protocol error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.1.1.16 flow control protocol error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.1.1.17 receiver overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.1.1.18 malformed tlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.1.2 forward transparent bridge pci/pci-x originating interface (secondary to primary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.1.2.1 received pci/pci-x errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.1.2.2 unsupported request (ur) completion status . . . . . . . . . . . . . . . . . . . . 135 8.1.2.3 completer abort (ca) completion status . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.1.2.4 split completion errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.1.3 forward transparent bridge timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.1.3.1 pci express completion timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.1.3.2 pci delayed transaction timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.1.4 forward transparent bridge serr# forwarding . . . . . . . . . . . . . . . . . . . . . . 141 8.2 reverse transparent bridge error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.2.1 reverse transparent bridge forwarding pex 8114 system errors and system error messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.2.1.1 root port error forwarding control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.2.1.2 conventional pci type 1 error forwarding control . . . . . . . . . . . . . . . . . 144 8.2.1.3 bridge-detected error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.2.2 reverse transparent bridge pci express originating interface (secondary to primary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8.2.2.1 received poisoned tlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.2.2.2 received ecrc error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.2.2.3 pci/pci-x uncorrectable data errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.2.2.4 pci/pci-x address/attribute errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
january, 2007 plx technology, inc. expresslane pex 8114bc pci express-to-pci/pci-x bridge data book xv copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.5 pci/pci-x master abort on posted transaction . . . . . . . . . . . . . . . . . . . 152 8.2.2.6 pci/pci-x master abort on non-posted transaction . . . . . . . . . . . . . . . 153 8.2.2.7 pci-x master abort on split completion . . . . . . . . . . . . . . . . . . . . . . . . . 154 8.2.2.8 pci/pci-x target abort on posted transaction . . . . . . . . . . . . . . . . . . . . 155 8.2.2.9 pci/pci-x target abort on non-posted transaction . . . . . . . . . . . . . . . . 156 8.2.2.10 pci-x target abort on split completion . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.2.2.11 unexpected completion received . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8.2.2.12 received request unsupported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.2.2.13 link training error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.2.2.14 data link protocol error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.2.15 flow control protocol error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8.2.2.16 receiver overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.2.2.17 malformed tlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.2.3 reverse transparent bridge pci/pci-x originating interface (primary to secondary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 8.2.3.1 received pci/pci-x errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.2.3.2 unsupported request (ur) completion status . . . . . . . . . . . . . . . . . . . . 173 8.2.3.3 completer abort completion status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 8.2.3.4 split completion errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8.2.4 reverse transparent bridge timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.2.4.1 pci express completion timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.2.4.2 pci delayed transaction timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . 181 8.2.5 reverse transparent bridge pci express error messages . . . . . . . . . . . . . . 182 chapter 9 serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.2 configuration data download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 chapter 10 interrupt handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.2 interrupt handler features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.3 events that cause interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10.4 intx# signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 10.5 message signaled interrupts (msi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 10.5.1 msi capability structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 10.5.2 msi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10.6 remapping inta# interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 chapter 11 pci/pci-x arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.2 arbiter key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.4 pex 8114 arbiter usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.5 external bus functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.6 detailed functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.6.1 bus parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 11.6.2 hidden bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 11.6.3 address stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
contents plx technology, inc. xvi expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 12 hot plug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 12.1 hot plug purpose and ca pabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.1.1 hot plug controller capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.1.2 hot plug port external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.1.3 hot plug typical hardware configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.1.4 hot plug sequence illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.1.5 pci express capabilities register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.1.6 hot plug interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.1.7 hot plug insertion and removal process . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 chapter 13 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 13.1 power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 13.2 pex 8114 power management cap abilities summary . . . . . . . . . . . . . . . . . . . . 205 13.2.1 general power management capa bilities . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 13.2.2 forward br idge-specific power management capab ilities . . . . . . . . . . . . . . 205 13.2.3 reverse transparent br idge-specific power manageme nt capabilities . . . . 206 13.2.4 device power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.2.4.1 d0 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.2.4.2 d3hot state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.2.4.3 d3cold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.2.5 link power management state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.2.6 pex 8114 pci express power management support . . . . . . . . . . . . . . . . . . 208 chapter 14 pex 8114 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14.2 type 1 pex 8114 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 14.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 14.4 type 1 configuration space header registers . . . . . . . . . . . . . . . . . . . . . . . . . . 221 14.5 power management capability regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 14.6 message signaled interrupt cap ability registers . . . . . . . . . . . . . . . . . . . . . . . . 241 14.7 pci-x capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.8 pci express capabilities registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 14.9 plx indirect configuration access mechanism registers . . . . . . . . . . . . . . . . . . 261 14.10 device serial number exten ded capability registers . . . . . . . . . . . . . . . . . . . . 262 14.11 device power budgeting exte nded capability registers . . . . . . . . . . . . . . . . . . 263 14.12 virtual channel exte nded capability registers . . . . . . . . . . . . . . . . . . . . . . . . . 265 14.13 plx-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.13.1 error checking and debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.13.2 physical layer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 14.13.3 cam routing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 14.13.3.1 bus number cam register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.13.3.2 i/o cam register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.13.3.3 amcam (address-mapping cam) registers . . . . . . . . . . . . . . . . . . . . 289 14.13.3.4 tic control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14.13.3.5 i/o cam base and limit upper 16 bits registers . . . . . . . . . . . . . . . . 291 14.13.4 base address registers (bars) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.13.5 ingress credit handler (inch) registers . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.13.5.1 inch threshold virtual channel registers . . . . . . . . . . . . . . . . . . . . . 294 14.13.6 internal credit handler (itch) vc&t threshold registers . . . . . . . . . . . . . 295 14.13.6.1 pci express interface plx-specific internal credit handler (itch) vc&t threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14.13.6.2 pci-x interface plx-specific internal credit handler (itch) vc&t threshold registers . . . . . . . . . . . 297
january, 2007 plx technology, inc. expresslane pex 8114bc pci express-to-pci/pci-x bridge data book xvii copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.14 pci-x plx-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 14.15 root port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14.16 pci-x-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 14.17 pci arbiter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14.18 advanced error reporting capa bility registers . . . . . . . . . . . . . . . . . . . . . . . . . 307 chapter 15 test and debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 15.1 physical layer loop-back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 15.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 15.1.2 loop-back test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.1.2.1 internal loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.1.2.2 analog loop-back master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 15.1.2.3 digital loop-back master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.1.2.4 analog loop-back slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 15.1.2.5 digital loop-back slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 15.2 pseudo-random and bit-pattern generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.3 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 15.3.1 ieee 1149.1 and 1149. 6 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . 325 15.3.2 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.3.3 jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 15.3.4 jtag reset input trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 chapter 16 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 16.2 pex 8114 power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 16.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 16.4 digital logic interface operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 331 16.4.1 serdes/lane interface dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 332 16.5 serdes interface ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 chapter 17 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.1 pex 8114 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.3 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 appendix a serial eeprom map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 a.1 serial eeprom map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 appendix b sample c code implementation of crc generator . . . . . . . . . . . . . . . . . . . 347 appendix c general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 c.1 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 c.2 united states and international representatives and distributors . . . . . . . . . . . . 350 c.3 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
contents plx technology, inc. xviii expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book xix copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 registers 14-1. 00h product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 14-2. 04h command/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 14-3. 08h class code and revision id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 14-4. 0ch miscellaneous control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 14-5. 10h base address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 14-6. 14h base address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 14-7. 18h bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 14-8. 1ch secondary status, i/o limit, and i/o base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 14-9. 20h memory base and limit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14-10. 24h prefetchable memory base and limit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14-11. 28h prefetchable memory upper base address[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 14-12. 2ch prefetchable memory upper limit address[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 14-13. 30h i/o base address[31:16] and i/o li mit address[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 14-14. 34h new capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 14-15. 38h expansion rom base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 14-16. 3ch bridge control and interrupt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 14-17. 40h power management capability list, capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 14-18. 44h power management status and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 14-19. 48h message signaled interrupt capability list, control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 14-20. 4ch lower message address[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 14-21. 50h upper message address[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 14-22. 54h message data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 14-23. 58h pci-x capability list, secondary status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 14-24. 5ch pci-x bridge status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 14-25. 60h upstream split transaction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 14-26. 64h downstream split transaction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 14-27. 68h pci express capability list, capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 14-28. 6ch device capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 14-29. 70h device status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 14-30. 74h link capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 14-31. 78h link status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 14-32. 7ch slot capabilities (reverse transparent bridge mode on ly). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 14-33. 80h slot status and control (reverse transparent bridge mode only) . . . . . . . . . . . . . . . . . . . . . . . . . .258 14-34. f8h configuration address window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 14-35. fch configuration data window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 14-36. 100h device serial number extended capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 14-37. 104h serial number (low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 14-38. 108h serial number (high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 14-39. 138h device power budgeting extended capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 14-40. 13ch data select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 14-41. 140h power data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 14-42. 144h power budget capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 14-43. 148h virtual channel budgeting extended capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 14-44. 14ch port vc capability 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 14-45. 150h port vc capability 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 14-46. 154h port vc status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 14-47. 158h vc0 resource capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 14-48. 15ch vc0 resource control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 14-49. 160h vc0 resource status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 14-50. 1c8h ecc check disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 14-51. 1cch device-specific error 32-bit erro r status (factory test only). . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 14-52. 1d0h device-specific error 32-bit error mask (factory test only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 14-53. 1e0h power management hot plug user configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 14-54. 1e4h egress control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
registers plx technology, inc. xx expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14-55. 1e8h bad tlp count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14-56. 1ech bad dllp count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14-57. 1f0h tlp payload length count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 14-58. 1f8h ack transmission latency limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 14-59. 210h test pattern_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14-60. 214h test pattern_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14-61. 218h test pattern_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14-62. 21ch test pattern_3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14-63. 220h physical layer status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 14-64. 224h port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 14-65. 228h physical layer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 14-66. 22ch physical layer (factory test only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 14-67. 230h physical layer port command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14-68. 234h skip ordered-set interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14-69. 238h quad serdes[0-3] diagnostics data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 14-70. 248h serdes nominal drive current select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 14-71. 24ch serdes drive current level_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 14-72. 254h serdes drive equalization level select_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14-73. 260h serial eeprom status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 14-74. 264h serial eeprom buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 14-75. 2e8h bus number cam 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14-76. 318h i/o cam_8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14-77. 3c8h amcam_8 memory limit and base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14-78. 3cch amcam_8 prefetchable memory limit and base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14-79. 3d0h amcam_8 prefetchable memory base[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14-80. 3d4h amcam_8 prefetchable memory limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14-81. 660h tic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14-82. 668h tic port enable (factory test only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14-83. 6a0h i/ocam_8 base and limit upper 16 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14-84. 700h bar0_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14-85. 704h bar1_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14-86. 9f4h inch fc update pending timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14-87. 9fch inch mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14-88. a00h inch threshold vc0 posted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14-89. a04h inch threshold vc0 non-posted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14-90. a08h inch threshold vc0 completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14-91. c00h pci express interface pci express itch vc&t threshold_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 14-92. c04h pci express interface itch vc&t threshold_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 14-93. f70h pci-x interface itch vc&t threshold_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14-94. f74h pci-x interface itch vc&t threshold_2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14-95. f80h pci-x interface device-specific error 32-bit error st atus (factory test only) . . . . . . . . . . . . . . . . 299 14-96. f84h pci-x interface device-specific error 32-bit error ma sk (factory test only). . . . . . . . . . . . . . . . . 300 14-97. f88h pci-x interface completion buffer timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14-98. f8ch root control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14-99. f90h root status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14-100. f94h root error command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14-101. f98h root error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 14-102. f9ch error identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 14-103. fa0h pci clock enable, strong ordering, read cycle value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 14-104. fa4h prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 14-105. fa8h arbiter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14-106. fach arbiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14-107. fb0h arbiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14-108. fb4h pci express enhanced capability header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14-109. fb8h uncorrectable error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14-110. fbch uncorrectable error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 14-111. fc0h uncorrectable error severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14-112. fc4h correctable error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 14-113. fc8h correctable error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
january, 2007 plx technology, inc. expresslane pex 8114bc pci express-to-pci/pci-x bridge data book xxi copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14-114. fcch advanced error capabilities and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 14-115. fd0h header log_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 14-116. fd4h header log_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 14-117. fd8h header log_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 14-118. fdch header log_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 14-119. fe0h secondary uncorrectable error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 14-120. fe4h secondary uncorrectable error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 14-121. fe8h secondary uncorrectable error severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 14-122. fech secondary uncorrectable error pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 14-123. ff0h ? ffch secondary header log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
registers plx technology, inc. xxii expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 1 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 1 introduction 1.1 features the plx expresslane tm pex 8114 pci express-to-p ci/pci-x bridge supports the following features: four full-duplex pci express lanes 8b/10b encoding, 2.5 gbps bandwidth four integrated serdes on bridge x1, x2, or x4 port lane width, established during link auto-negotiation lane reversal lane polarity inversion link power management states ? l0, l0s, l1, l2/l3 ready, and l3 pci express 256-byte maximum payload size read completion supported for all eight (8) traffic classes one virtual channel (vc0) tlp digest end-to-end crc checking data poisoning baseline and advanced error reporting capability spi/serial eeprom for initialization jtag pci bus clock master and slave data rates ? conventional pci ? 25, 33, 50, and 66 mhz ? pci-x ? 50, 66, 100, and 133 mhz arbitration ? internal arbitration (four req/gnt external pairs) that can be enabled or disabled ? external arbitration accepted message signaled interrupts (msi) 64-bit data width dual address cycles (dac) 64-bit addressing as master and slave maximum 4-kb master writes and reads on pci-x bus eight outstanding split transactions on primary side, and eight outstanding split transactions on secondary side address stepping and idsel stepping one type 1 configuration space header forward and reverse transparent bridge modes (primary or secondary interface) all completions to pci express transactions are assigned to the traffic class on which they originated clocks up to four external pci/pci-x devices prefetchable memory address range
introduction plx technology, inc. 2 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 transaction ordering and deadlock avoidance rules oversubscribe and flood modes ecc checking on destination packet ram standard 256-ball pbga package (17 x 17 mm) compliant to the following specifications: ? pci local bus specification, revision 2.3 (pci r2.3) ? pci local bus specification, revision 3.0 (pci r3.0) ? pci express card electromechanical (cem) specification, revision 1.0a (pci expresscard cem r1.0a) ? pci express card electromechanical (cem) specification, revision 1.1 (pci 2.0 cem r1.1) ? pci to pci bridge architecture specification, revision 1.1 (pci-to-pci bridge r1.1) ? pci bus power management interface specification, revision 1.2 (pci power mgmt. r1.2) ? pci hot plug specification, revision 1.1 (pci hotplug 1.1) ? pci standard hot plug controller and subsystem specification, revision 1.0 (hot plug r1.0) ? pci-x addendum to pci local bus speci fication, revision 1.0b (pci-x r1.0b) ? pci-x addendum to pci local bus speci fication, revision 2.0a (pci-x r2.0a) ? pci express base specification, revision 1.0a (pci express base 1.0a) ? pci express to pci/pci-x bridge specification, revision 1.0 (pci express-to-pci /pci-x bridge r1.0) ? ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture, 1990 (i eee standard 1149.1-1990) ? ieee standard 1149.1a-1993, ieee standard test access port and boundary-scan architecture (ieee standard 1149.1-1993) ? ieee standard 1149.1b-1994, specifications for ven dor-specific extensions (ieee standard 1149.1-1990) ? ieee standard test access port and bo undary-scan architecture extensions (ieee standard 1149.6-2003)
january, 2007 pex 8114 serial pci express to pci/pci-x bridge expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 3 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.2 pex 8114 serial pci expr ess to pci/pci-x bridge the pex 8114 is a high-performance bridge that enables designers to migrate conventional pci and pci-x bus interfaces to the new advanced serial pci express. this simple two-port device is equi pped with a standard, but flexible, pci express port that scales from 2.5 to 10 gbps maximum bit rate. supporting stan dard pci express signaling, these bandwidths are achieved with the lowest possible ball count (16 balls), using lvds technology. the single parallel bus segment supports the advanced pci-x protocol. conventional pci and pci-x interfaces can reach 8-gbps bandwidth, using a 64-bit wide parallel data path at a clock frequency of 133 mhz. while both sides of the bridge are evenly matched, the pex 8114 also supports internal queues with flow control (fc) features to optimize throughput and traffic flow. the pex 8114 is available in a standard 256-ball plastic ball grid array (b ga) package. the small footprint and low-power consumption make the pex 8114 an ideal bridge for use on adapter board, daughter board, add-on module, and backplane designs, as well as on larger planar boards. figure 1-1. pex 8114 ? two-port device pex 8104 pex 8114 pci express link pci/pci-x bus segment
introduction plx technology, inc. 4 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.2.1 introduction to pex 8114 operation the pex 8114 is a pci express-to-pci-x bridge that provides a functional link from a pci or pci-x bus segment to a pci express port. this port ca n be configured as x1, x2, or x4 2.5 gbps lanes. the pci express port conforms to the pci express r1.0a. data received by the pci/pci-x input from an external pci/pc i-x bus is delivered to the pci express port. there are several data transfer modes that the pe x 8114 supports as it transfers data between pci-x and pci express.the pex 8114 can operate as a forwar d or reverse bridge (by way of ball strap). as a forward bridge , configuration accesses are transmitte d from the pci express root complex as a reverse bridge , configuration accesses are tran smitted from the pci-x bus in addition to forward and reverse bridging, the pex 8114 also operates as a transparent bridge: ? if a type 1 configuration access is seen, if it matches the host secondary bus, the type 1 configuration access is changed to a type 0 configuration access and accepted ? if the type 1 configuration access is for some destination further down the bus hierarchy, the type 1 configuration access is maintained an d passed along figure 1-2 provides a pex 8114 top-level block diagram. figure 1-2. pex 8114 top-level block diagram pci or pci-x bus segment pci/pci-x module pci express module pci/pci-x bus x1, x2, x4 pci express port pex 8114 25, 33, 50, 66, 100, 133 mhz hot plug (pci express client only) power management serial eeprom pci 4-input arbiter multiple lanes
january, 2007 detailed block diagram expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 5 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.3 detailed block diagram figure 1-3 illustrates pex 8114 implementation, with the modules at the data transfer core. other modules, such as the pci-x arbiter and power management, are not included in figure 1-3 . figure 1-3. pex 8114 top-level detailed block diagram pci/pci-x bus segment tlce de crossing desti- nation source is crossing source de crossing desti- nation tlce tlci dll phy is crossing p o r t pci/pci-x pci express crossbar pci/pci-x module either conventional pci or a pci-x bus segment interface interface
introduction plx technology, inc. 6 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.3.1 physical layer ? layer 1 layer 1 ? physical layer (phy) ? defines the pci express electrical characteristics. the basic transmission unit consists of two pairs of wires, called a lane . each pair is equipped with unidirectional data transmission at 2.5 gbps, allowing the two wire pairs, when combined, to provide 2.5 gbps full-duplex communication, without the risk of transmission collision. 1.3.2 data link layer ? layer 2 layer 2 ? data link layer (dll) ? defines the pci express data control. the data link layer provides link management and data integrity, including error detection and correction. this layer calculates and appends a cyclic redundancy check (crc) and sequ ence number to the information transmitted from the data packet. the crc verifies that data from link to link is correctly transmitted 1 . the sequence number allows proper data packet ordering. 1.3.3 transaction layer ? layer 3 layer 3 ? transaction layer (tl) ? connects the lower protocols to the upper layers. this layer appears to the upper layers as pci . the transaction layer packetizes and prepends a header to the payload data. write and read commands, as well as prior sideband signals, such as interrupts and power management requests, are also included in this layer. to achieve code compatibility with pci, pci express does not modify the transaction layer. this is significant because it allows vendor s to leverage their existing pci code to achieve not only a faster time to market, using their proven design, it also provides a more stable and mature platform. 1. to ensure end-to-end data integrity, there is an optional feature in the pci express r1.0a. this feature is called tlp digest and is defined in layer 3.
january, 2007 sample paths expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 7 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.3.4 sample paths 1.3.4.1 forward transpa rent bridge mode in forward transparent bridge mode , the configuration cycles orig inate from the pci express link, by way of the pex 8114 bridge and out to the pci/pci-x bus segment (conventional pci or pci-x). as a forward bridge, all configuration accesses ar e transmitted from the pci express root complex. figure 1-4. pex 8114 as a forward bridge switch pci express device pci express device pci/pci-x device 0 pci/pci-x device 1 pci/pci-x device n pci/pci-x pci express bus segment o o o pex 8114 host tlp configuration pci/pci-x configuration
introduction plx technology, inc. 8 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.3.4.2 reverse transparent bridge mode in reverse transparent bridge mode , the configuration cycles orig inate from the pci/pci-x bus segment (conventional pci or pci-x), by way of th e pex 8114 bridge and out to the pci express link. as a reverse bridge, all configuration accesses originate from the pci/pci-x bus. figure 1-5. pex 8114 as a reverse bridge pci express device pci express device pci express device pci/pci-x pci express pci/pci-x device 1 pci/pci-x device n pex 8114 host tlp configuration pci/pci-x configuration switch o o o
january, 2007 pex 8114 applications expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 9 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.4 pex 8114 applications various pex 8114 applications are as follows: pci express adapter board pci express motherboard to pci-x expansion slot pci-x host supporting a pci express expansion slot pci-x add-in board created from pci express native silicon pci-x extender board 1.4.1 pci express adapter board in a pci express adapter board application, the pe x 8114 is installed on a pci express adapter board, allowing a conventional pci or pci-x device to cr eate a pci express board. this configuration is illustrated in figure 1-6 , wherein the pex 8114 is a forward transparent bridge . figure 1-6. pci express board created from pci/pci-x native silicon pex 8114 pci or pci-x native design pci-x bus pci express port forward transparent pci express adapter board pci express connector
introduction plx technology, inc. 10 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.4.2 pci express motherboar d to pci-x expansion slot in a pci express motherboard to pci-x expansion slot application, the pex 8114 is used on the motherboard to support standard pci-x add-in board slots. it is similar to the pci express adapter board mode, as it allows a pci express root-based processor system to accept conventional pci or pci-x silicon. the configuration is illustrated in figure 1-7 , wherein the pex 8114 is a forward transparent bridge. an entire pci-x bus segment with standard pci-x add-in boards can be supported in this mode. the pex 8114?s simple design and small footprint make it an ideal bridge solution for the motherboard, providing for pci r3.0 or pci-x r1.0b slot connectivity or interface to native pci or pci-x silicon i/o components on the motherboard. figure 1-7. pex 8114 on motherbo ard provides pci/pci-x slots root complex (pci express native) pci express ports pci express native component p-bridge pci express link (x1, x2, x4) pci or pci-x add-in board slots motherboard pci express link p-bridge pex 8114 host cpu forward transparent
january, 2007 pci-x host supporti ng a pci express expansion slot expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 11 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.4.3 pci-x host supporting a pci express expansion slot in a pci-x host supporting a pci express expans ion slot application, the pex 8114 is used as a reverse transparent bridge on a pci-x motherboard to create pci express links. the configuration is illustrated in figure 1-8 , wherein the pex 8114 is a reverse transparent bridge . figure 1-8. pci-x host using pex 8114 to create pci express board slot pci express link pci-x bus reverse transparent pci-x host board or motherboard pex 8114 board slot pci/pci-x host
introduction plx technology, inc. 12 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.4.4 pci-x add-in board create d from pci express native silicon a pci-x add-in board creat ed from pci express native silicon application enables adapter boards based on state-of-the-art pci express silicon to plug into pci/pci-x motherboard expansion slots. the configuration is illustrated in figure 1-9 , wherein the pex 8114 is a reverse transparent bridge . figure 1-9. pci-x adapter board created using pex 8114 and pci express native silicon pex 8114 pci express link pci express native silicon pci-x bus reverse transparent
january, 2007 pci-x extender board expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 13 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1.4.5 pci-x extender board a pci-x extender board application uses the pe x 8114 to create a bridge board, enabling pci or pci-x bus expansion over standardized pci e xpress cabling. the config uration is illustrated in figure 1-10 , wherein the pex 8114 is a reverse transparent bridge . figure 1-10. pci-x adapter board acti ng as bridge board for bus expansion pex 8114 pci express link pci-x bus reverse transparent pci express cable connector
introduction plx technology, inc. 14 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 15 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 2 signal ball description 2.1 introduction this chapter provides descriptions of the 256 pex 8114 signal balls. the signals are divided into the following groups: pci/pci-x bus interface signals pci express in terface signals hot plug signals strapping signals jtag interface signals serial eeprom interface signals power and ground signals the signal name, type, location, and a brief desc ription are provided fo r each signal ball.
signal ball description plx technology, inc. 16 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.2 abbreviations the following abbreviations are used in the signal tables provided in this chapter. note: depending on the strapping configuration, certain balls change type. this is indicated in the type column and descriptive fiel d for the associated balls. table 2-1. ball assignment abbreviations abbreviation description # active-low signal apwr 1.0v power (vdd10a) ball s for serdes analog circuits cpwr 1.0v power (vdd10) balls for low-voltage core circuits dpwr 1.0v power (vdd10s) balls for serdes di gital circuits gnd ground i cmos input i/o cmos bi-direc tional input/output i/opwr 3.3v power (vdd33) balls for input and output interfaces lvdsrn differential low-vo ltage, high-speed, lvds negative receiver inputs lvdsrp differential low-vo ltage, high-speed, lvds positive receiver inputs lvdstn differential low-voltage, high-spee d, lvds negative transmitter outputs lvdstp differential low-voltage, high-sp eed, lvds positive transmitter outputs o cmos output od open drain output pci pci/pci-x compliant pllpwr 3.3v power (vdd33a ) balls for pll circuits pu signal is internally pulled up strap strapping balls must be tied to hi gh to vdd33 or low to vss on the board sts pci/pci-x sustained three-state output , driven high for one clk before float tp totem pole ts three-state bi-directional
january, 2007 pull-up resistors expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 17 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.2.1 pull-up resistors the balls defined in table 2-2 have weak internal pull-up resistor values. therefore, it is strongly advised that an external pull-up resistor to vdd33 (3k to 10k ohms is recommended) be used on those signal balls when implemented in a design. for the remaining balls listed in this section, depending upon the application, certain balls are driven, pulled or tied, high or low. when the pci_pme# ball is not used, it requires an external pull-up resistor. when the internal pci arbiter is not used (disabled), the pci_req[3:1]# inputs require external pull-up resistors. if the internal pci arbiter is used (ena bled), the pci_req[3:0]# balls must be driven, pulled, or tied to a known state. because the pci_gnt[3:0]# outputs are driv en, regardless of whether the pci arbiter is enabled, they do not require external pull-up resistors, and can be connected or remain unconnected (floating). for information on hot plug systems, refer to the pci express-to-pci/pci-x bridge r1.0 for ball connection and usage. for non-hot plug systems, the hot plug input balls defined in table 2-5 can remain unconnected, as each has its own internal pull-up resistor. serial eeprom interface balls ee_cs#, ee_di, an d ee_sk are outputs that are driven by the pex 8114, and can be connected or remain unconnected (floating) . serial eeprom interface balls, ee_do is an input with an internal pull-up resistor. drive, pull, or tie this input to a known state. for designs that do not implement jtag, ground the jtag_trst# ball and drive, pull, or tie the jtag_tck input to a known value. jtag_tdi, jtag_tms, and jtag_tdo can remain unconnected. table 2-2. balls with internal pull-up resistors ball name ee_do jtag_tck hp_button# jtag_tdi hp_mrl# jtag_tms hp_prsnt# jtag_trst# hp_pwrflt#
signal ball description plx technology, inc. 18 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.3 pci/pci-x bus interface signals the pci balls defined in table 2-3 do not contain internal resist ors and are generic primary and secondary pci/pci-x interface balls. when produci ng motherboards, system slot boards, adapter boards, backplanes, and so forth, the termination of these balls must follow the guidelines detailed in the pci r3.0 and pci-x r1.0b . the following guidelines are not exhaus tive; therefore, read in conjunction with the appropriate pci r3.0 and pci-x r1.0b sections. pci control signals require a pull-up resistor on the mo therboard to ensure that these signals are at valid values when a pci bus agent is not drivin g the bus. these control signals include pci_ack64# , pci_devsel# , pci_frame# , pci_int[d:a]# , pci_irdy# , pci_perr# , pci_req64# , pci_serr# , pci_stop# , and pci_trdy# . the 32-bit point-to-point and shared bus signals do not require pull-up resistors, as bus parking ensures that these signals remain stable. the other 64-b it signals ? pci_ad[63:32], pci_c/be[7:4]#, and pci_par64 ? also require pull-up resistor s, as these signals are not driv en during 32-bit transactions. the pci_int[d:a]# balls require pull-up resistors, regardless of whether they are used. in forward transparent bridge mode, pci_idsel is not used and requires a pull-up resistor. depending on the application, pci_m66en can also require a pull-up resistor. the value of these pull-up resistors depends on the bus loading. the pci r3.0 provides formulas for calcula ting the resistor values. when making adapter board devices where the pex 8114 port is wired to the pci connector, pull-up resistors are not required because they are pre-installed on the motherboard. based on the above, in an embedded design, pull-up re sistors can be required for pci control signals on the bus. the pex 8114 includes 108 pci/pci-x signals, which are defined in table 2-3 . the categories included in the type columns of certain of these signals are from the pci express-to-pci/pci-x bridge r1.0 , tables 6-3 and 6-4. by convention, multiple balls are listed in high-to-low order ( that is , pci_ad63, pci_ad62, ?, pci_ad0).
january, 2007 pci/pci-x bus interface signals expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 19 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 table 2-3. pci/pci-x bus interface signals (108 balls) symbol type location description pci_ack64# i/o sts pci a13 64-bit transfer acknowledge asserted by the pci slave in response to pci_req64# , to acknowledge a 64-bit data transfer. 0 = acknowledges a 64-bit transfer 1 = no acknowledge pci_ad[63:0] i/o ts pci a15, c15, a16, d14, b16, d15, c16, e13, d16, e14, e15, f13, e16, f14, f16, g13, g16, g14, h15, h13, h16, h14, j15, j13, j16, j14, k15, k13, k16, k14, l16, l14, f1, f3, e1, f4, d1, e3, d2, d3, b1, c2, a1, c3, a2, d4, b3, c4, c7, a7, d8, a8, c8, a9, d9, b10, a10, c10, b11, d11, a11, c11, a12, c12 address and data (64 balls) pci multiplexed address/data bus. pci_c/be[7:0]# i/o ts pci c13, a14, d13, b14, c1, a3, b7, d10 bus command and byte enables (8 balls) during the pci and/or pci-x address phase, pci_c/be[3:0]# provide the command type. during the data phase of pci and/or pci-x memory write transactions, pci_c/be[7:0]# provide byte enables. during the pci-x attribute pha se, pci_c/be[7:0]# provide a portion of the attribute information. pci_clk i pci j1 pci/pci-x bus clock input clock reference when strap_clk_mst =0. not the clock reference when strap_clk_mst=1. (refer to chapter 3, ?clock and reset,? for further details.) pci_clko[3:0] o pci l1, l2, k1, k3 clock outputs (4 balls) pci/pci-x bus clocks for up to four devices. derived from pex_refclkn/p . (refer to chapter 3, ?clock and reset,? for further details.) pci_clko_dly_fbk o pci n3 pci clock delayed feedback pci/pci-x clock intended to be fed back to the pex 8114 pci_clk input ball when strap_clk_mst and strap_ext_clk_sel are high. the trace length provides a time phase delay on the pci clock that drives the internal pci circuitry, thereby aligning the in ternal pci_clk ri sing edge with the clock edges of other pci devices on the pci bus that can be sufficiently separated physically, such that clock-phase alignment becomes necessary. pci_devsel# i/o sts pci a4 device select when actively driven, indicate s the driving device decoded its address as the target of the current access. pci_frame# i/o sts pci d5 frame driven by the transaction initiator to indicate an access start and duration. while pci_frame# is asserted, data transfers continue.
signal ball description plx technology, inc. 20 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pci_gnt# or pci_gnt0# i/o ts pci g3 grant or internal pci arbiter grant 0 pci_gnt# (input): when the pex 8114 internal pci arbiter is disabled, this is a pci/ pci-x bus grant from the external arbiter. pci_gnt0# (output): when the pex 8114 internal pci arbiter is enabled, pci_gnt0# is an output to an arbitrating master. the pex 8114 arbiter asserts pci_gnt0# to grant the pci/pci-x bus to the master. pci_gnt[3:1]# o tp pci j3, j4, h3 internal pci arbiter grants 3 to 1 (3 balls) when the pex 8114 internal pci arbiter is enabled, pci_gnt[3:1]# are outputs (one ea ch) to an arbitrating master. the internal pci arbiter asserts pci_gnt[3:1]# to grant the pci/ pci-x bus to the corresponding master. pci_idsel i pci e4 device select forward transparent bridge mode: pci_idsel is not used and requires a pull-up resistor. reverse transparent bridge mode: used as a chip select during configuration write and read transactions. pci_int[d:a]# i/o od pci m2, k4, m1, l3 interrupts d, c, b, and a (4 balls) forward transparent bridge mode: pci/pci-x bus interrupt inputs. reverse transparent bridge mode: pci/pci-x bus interrupt outputs. pci_irdy# i/o od pci b4 initiator ready pci/pci-x bus initiator ready. indicates initiating agent?s (bus master) ability to complete the current data phase of the transaction. pci_m66en i pci b9 pci bus clock speed capability indicator refer to table 3-3 . pci_par i/o ts pci d7 parity even parity across pci_ad[31:0] and pci_c/be[3:0]#. pci_par is stable and valid one clock after the address phase. for data phases, pci_par is st able and valid one clock after pci_irdy# is asserted on a write transaction or pci_trdy# is asserted on a read transaction. after pci_par is valid, it remains valid until one clock after the current data phase completes. pci_par64 i/o ts pci c14 upper 32 bits parity even parity across pci_ad[ 63:32] and pci_c/be[7:4]#. pci_par64 is stable and valid one clock after the address phase. for data phases, pci_par64 is st able and valid one clock after pci_irdy# is asserted on a wr ite transaction or pci_trdy# is asserted on a read transaction. after pci_par64 is valid, it remains valid until one clock after the current data phase completes. table 2-3. pci/pci-x bus interface signals (108 balls) (cont.) symbol type location description
january, 2007 pci/pci-x bus interface signals expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 21 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pci_pcixcap i a5 pci-x capability used with pci_pcixcap_pu to determine whether all devices running on the pci/pci-x bus are capable of running pci-x cycles and at which frequency. clock master mode: connect the pci_pcixcap_pu ball to the pci_pcixcap ball through a 1k-ohm resistor wh en operating at pci 66, and pci-x 66 and 133. a 56k-ohm resistor between vdd33 and the pci_pcixcap ball is also required. pci_pcixcap_pu o c5 pci/pci-x bus pci_pcixcap pull-up driver used with pci_pcixcap to determine whether all agents on the pci/pci-x bus are pci-x-compati ble in clock master mode. clock master mode: connect the pci_pcixcap_pu ball to the pci_pcixcap ball through a 1k-ohm resistor wh en operating at pci 66, and pci-x 66 and 133. pci_perr# i/o sts pci b6 parity error pci/pci-x bus parity error i ndicator. reports and records data parity errors during all pc i transactions, except during a special cycle. pci_pme# i/o ts pci g4 power management event forward transparent bridge mode: pci/pci-x bus power management event (pme) indicator input. reverse transparent bridge mode: pci/pci-x bus power manageme nt event indicator output. pci_req# or pci_req0# i/o pci g2 request or internal pci arbiter request 0 pci_req# (output): when the pex 8114 internal pci arbiter is disabled, this is a pci/pci-x bus request to the external arbiter. pci_req0# (input): when the pex 8114 internal pci arbiter is enabled, pci_req0# is an input from an arbitrating master. the internal pci arbiter asserts pci_gnt0# to grant the pci/ pci-x bus to the master. pci_req[3:1]# i pci h1, h2, g1 internal pci arbiter requ ests 3 to 1 (3 balls) when the pex 8114 internal pci arbiter is enabled, pci_req[3:1]# are inputs (one ea ch) from an arbitrating master. the internal pci arbiter asserts a pci_gnt[3:1]# signal to grant the pci/pci-x bus to the corresponding master. pci_req64# i/o sts pci d12 64-bit transfer request asserted (0) with pci_frame# by a pci bus master to request a 64-bit data transfer. forward transparent bridge or clock master mode: the pex 8114 asserts pci_req64# during pci_rst# to configure a 64-bit backplane. reverse transparent bridge mode and not clock master: the pex 8114 samples pci_req64# at pci_rst# de-assertion to configure a 32- or 64-bit pci backplane. table 2-3. pci/pci-x bus interface signals (108 balls) (cont.) symbol type location description
signal ball description plx technology, inc. 22 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pci_rst# i/o pci h4 reset forward transparent br idge mode, output: provides the pci/pci-x bus reset. the pex 8114 drives pci_rst# and asserts pci_rst# during the initialization period. reverse transparent bridge mode, input: receives the external reset signal from the bus. (refer to chapter 3, ?clock and reset,? for further details.) input that receives reset from an upstream host and is the equivalent of hot reset interna lly and causes the propagation of hot reset across the pci express link. pci_sel100 i m4 bus 100-mhz indicator when the pci/pci-x bus is ope rating in pci-x clock master mode in forward or reverse transparent bridge mode, or clock slave mode in forward transparent bridge mode: 0 = 133-mhz pci-x bus capability 1 = 100-mhz pci-x bus capability in clock slave mode, pull pci_sel100 high or low. pci_serr# i/o od pci a6 bus system error indicator input: assertion detected by the host , indicates a pci system error occurred. output: asserted by a target, indicates a fatal or non-fatal pci express parity error occurred. pci_stop# i/o sts pci c6 stop asserted by the target to signal to end the transaction on the current data phase. pci_trdy# i/o sts pci d6 target ready driven by the transaction target to indicate its ability to complete the current data phase. table 2-3. pci/pci-x bus interface signals (108 balls) (cont.) symbol type location description
january, 2007 pci express interface signals expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 23 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.4 pci express interface signals the pex 8114 includes 23 pc i express port interface signals, which are defined in table 2-4 . the port signals are low-voltage differential signal form at that requires two balls for each lane, in each direction. the four pex_lane_good x # signals are used to drive le ds to indicate the status of each lane. table 2-4. pci express interface signals (23 balls) symbol type location description pex_lane_good[3:0]# o r 16, t16, r15, t15 pci express lane status indicators (4 balls) 0 = lane active (led is on) 1 = lane inactive (led is off) pex_pern[3:0] i(-) lvdsrn m11, m9, m7, m5 negative half of pci expr ess receiver differential signal pairs (4 balls) pex_perp[3:0] i(+) lvdsrp n11, n9, n7, n5 positive half of pci express receiver differential signal pairs (4 balls) pex_petn[3:0] o(-) lvdstn t11, t9, t7, t5 negative half of pci express transmitter differential signal pairs (4 balls) pex_petp[3:0] o(+) lvdstp r11, r9, r7, r5 positive half of pci express transmitter differential signal pairs (4 balls) pex_perst# i t1 pci express reset used to cause a fundamental reset. in forward transparent bridge mode, pex_perst# is a 3.3v input with a weak internal pull-up resistor. (refer to chapter 3, ?clock and reset,? for further details.) pex_refclkn i(-) lvdsn r3 negative half of 100-mhz pc i express reference clock signal pair (refer to chapter 3, ?clock and reset,? for details.) pex_refclkp i(+) lvdsp t3 positive half of 100-mhz pc i express reference clock signal pair (refer to chapter 3, ?clock and reset,? for details.)
signal ball description plx technology, inc. 24 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.5 hot plug signals the pex 8114 includes nine hot plug signals for the pci express port, defined in table 2-5 . table 2-5. hot plug signals (9 balls) symbol type location description hp_atnled# o t14 hot plug attention led slot control logic output used to drive the attention indicator. set low to turn on the led. high/off = standard operation low/on = operational problem at this slot blinking = slot is identi fied at the user?s request blinking frequency = 2.0 hz, 50% duty cycle hp_button# i pu t13 hot plug attention button slot control logic input directly conne cted to the attention button, which is pressed to request hot plug ope rations. can be implemented on the bridge or downstream device. hp_clken# o r14 clock enable reference clock enable output. enabled when the slot capabilities register power controller present bit is set (offset 7ch[1]=1), and controlled by the slot control register power controller control bit (offset 80h[10]). the time delay from hp_pwren# (a nd hp_pwrled#) output assertion to hp_clken# output assertion is pr ogrammable from 16 ms (default) to 128 ms, in the hpc t pepv delay field (offset 1e0h[4:3]). hp_mrl# i pu r13 manually operated retention latch sensor slot control logic and power contro ller input directly connected to the mrl sensor. manually operated retenti on latch switch signal for inserting and extracting hot plug-capable boards. high = board is not available or properly seated in slot low = board not properly seated in slot hp_perst# o p14 reset hot plug reset for downstream link. enabled by the slot control register power controller control bit (offset 80h[10]). hp_prsnt# i pu p13 pci present input connected to external logic th at directly outputs prsnt# from the external combination of prsnt1# and prsnt2#. hp_pwren# o n14 power enable slot control logic output that cont rols the slot power state. when hp_pwren# is low, power is enabled to the slot. hp_pwrflt# i pu n13 power fault input indicates that the slot power controlle r detected a power fault on one or more supply rails. hp_pwrled# o m13 power led slot control logic output used to dr ive the power indicator. this output is set low to turn on the led.
january, 2007 strapping signals expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 25 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.6 strapping signals the eight pex 8114 strapping signals, defined in table 2-6 , set the configuration of forward and reverse transparent bridge mode, clock master and ar biter master selection, as well as various setup and test modes. these balls must be tied high to vdd33 or low to vss. table 2-6. strapping signals (8 balls) symbol type location description strap_arb i strap l5 arbiter select internal or external pci/pci-x ar biter select. strapping signal that enables and disables the pex 8114 pci/pci-x internal pci arbiter. 1 = enables the arbiter 0 = disables the arbiter (refer to chapter 11, ?pci/pci-x arbiter? ) strap_clk_mst i strap l4 clock master select in clock master mode, the 100-mhz pex_refclkn/p signals are used to generate a clock of 25, 33, 50, 66, 100, or 133 mhz on the pci_clko[3:0] balls. the clock frequency is determined by the pci_pcixcap , pci_m66en clock, and pci_sel100 ball states. (refer to table 3-3 .) 1 = pex 8114 is the pci_clk generator (clock master mode) 0 = pex 8114 is the pci_clk receiver (clock slave mode) strap_ext_clk_sel i strap n6 external pci clock select when the pex 8114 is in clock mast er mode and this ball is low, the pci clock is driven from the internal pci clock frequency generator to the internal pci module by way of a fed back clock signal. in this case, the pci_clk ball need not be driven by a clock signal, but pulled to a known level by external circuitry. when the strap_ext_clk_sel and strap_clk_mst balls are high, the pci clock must be driven externally from the pci_clko_dly_fbk output to the pci_clk input. the trace length and delay from pci_clk mu st match the length of other pcb trace driven from pci_clko[3:0] to external pci devices. strap_fwd i strap p16 forward transparent bridge mode select strapping signal that selects between forward and reverse transparent bridge modes. 1 = forward transparent bridge mode 0 = reverse transparent bridge mode strap_pll_bypass# i strap p3 pll bypass factory test only tied high for standard operation. strap_testmode[1:0] i strap t2, r2 test mode select (2 balls) factory test only tied high for standard operation. strap_tran i strap p15 transparent mode select strapping signal that sele cts transparent mode. note: value is always 1. 1 = transparent mode 0 = reserved
signal ball description plx technology, inc. 26 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.7 jtag interface signals the pex 8114 includes five signals for performing jtag boundary scan, defined in table 2-7 . for further details, refer to chapter 15, ?test and debug.? table 2-7. jtag interface signals (5 balls) symbol type location description jtag_tck i pu p1 test clock input clock source for the pex 8114 test ac cess port (tap). jtag_tck can be any frequency from 0 to 10 mhz. jtag_tdi i pu n2 test data input used to input data into the tap. when the tap enables this ball, it is sampled on the rising edge of jtag_tck and the sampled value is input to the selected tap shift register. jtag_tdo o n1 test data output used to transmit serial data from th e pex 8114 tap. data from the selected shift register is shifted out of jtag_tdo. jtag_tms i pu p2 test mode select sampled by the tap on the rising e dge of jtag_tck. the tap state machine uses the jtag_tms ball to determine the tap mode. jtag_trst# i pu r1 test reset resets jtag. toggle or hold at 0 for the pex 8114 to properly function. resets the tap.
january, 2007 serial eepr om interface signals expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 27 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.8 serial eeprom interface signals the pex 8114 includes five signals for interfacing to a serial eeprom, defined in table 2-8 . ee_do requires a weak internal pull-up resistor. table 2-8. serial eeprom in terface signals (5 balls) symbol type location description ee_cs# o n15 serial eeprom active-low chip select output weakly pulled up. can remain floating if not used or use a stronger pull-up resistor (5k to 10k ohms). ee_di o m16 serial eeprom data in pex 8114 output to the serial eeprom data input. weakly pulled up. can remain floating if not used or use a stronger pull-up resistor (5k to 10k ohms). ee_do i pu n16 serial eeprom data out pex 8114 input from the seri al eeprom data output. weakly pulled up. can remain floating if not used or use a stronger pull-up resistor (5k to 10k ohms). ee_pr# i l13 serial eeprom active-low present input when a serial eeprom is not used, must be pulled up to vdd33. 5k- to 10k-ohm pull-up resistor recommended. must be connected to vss if a serial eeprom is present and used. ee_sk o m14 7.8-mhz serial eeprom clock for a pci-x clock greater than 66 mhz, a 10-mhz serial eeprom is needed. for clock rates of 66 mhz and lower, a 5-mhz serial eeprom is sufficient. weakly pulled up. can remain floating if not used or use a stronger pull-up resistor (5k to 10k ohms).
signal ball description plx technology, inc. 28 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.9 power and ground signals table 2-9. power and ground signals (98 balls) symbol type location description vdd10 cpwr e6, e8, e9, e11, f5, f12, g5, g12, j5, j12, k5, k12, m6, m10, m12 core supply voltage (15 balls) 1.0v power for core logic v core . vdd10a apwr m8 serdes analog supply voltage 1.0v power for serdes analog circuits. vdd10s dpwr p8, r4, r6, r8, r10, r12 serdes digital supply voltage (6 balls) 1.0v power for serdes digital circuits. vdd33 i/opwr b2, b8, b12, b15, e5, e7, e10, e12, f2, g15, h5, h12, j2, l12, m3, m15, p12 i/o supply voltage (17 balls) 3.3v power for i/o logic functions v ring . vdd33a pllpwr p4 pll analog supply voltage 3.3v power for pll circuits. vss gnd b5, b13, c9, e2, f6, f7, f8, f9, f10, f11, f15, g6, g7, g8, g9, g10, g11, h6, h7, h8, h9, h10, h11, j6, j7, j8, j9, j10, j11, k2, k6, k7, k8, k9, k10, k11, l6, l7, l8, l9, l10, l11, l15, n8, n10, n12, p5, p6, p7, p9, p10, p11, t4, t8, t12 digital ground connections (55 balls) vssa gnd n4 analog ground connection vtt_pex[1:0] supply t10, t6 serdes termination supply (2 balls) tied to serdes termination supply voltage (typically 1.5v). a a. pex_petn/p[x] serdes termination supply voltage controls the transmitter common mode voltage (v tx?cm ) value and output voltage swing (v tx?diffp ), per the following formula: v tx-cm = v tt ? v tx?diffp
january, 2007 ball assignments by location expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 29 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.10 ball assignments by location table 2-10. ball assignments by location location signal name a1 pci_ad21 a2 pci_ad19 a3 pci_c/be2# a4 pci_devsel# a5 pci_pcixcap a6 pci_serr# a7 pci_ad14 a8 pci_ad12 a9 pci_ad10 a10 pci_ad7 a11 pci_ad3 a12 pci_ad1 a13 pci_ack64# a14 pci_c/be6# a15 pci_ad63 a16 pci_ad61 b1 pci_ad23 b2 vdd33 b3 pci_ad17 b4 pci_irdy# b5 vss b6 pci_perr# b7 pci_c/be1# b8 vdd33 b9 pci_m66en b10 pci_ad8 b11 pci_ad5 b12 vdd33 b13 vss b14 pci_c/be4# b15 vdd33 b16 pci_ad59 c1 pci_c/be3# c2 pci_ad22 c3 pci_ad20 c4 pci_ad16
signal ball description plx technology, inc. 30 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 c5 pci_pcixcap_pu c6 pci_stop# c7 pci_ad15 c8 pci_ad11 c9 vss c10 pci_ad6 c11 pci_ad2 c12 pci_ad0 c13 pci_c/be7# c14 pci_par64 c15 pci_ad62 c16 pci_ad57 d1 pci_ad27 d2 pci_ad25 d3 pci_ad24 d4 pci_ad18 d5 pci_frame# d6 pci_trdy# d7 pci_par d8 pci_ad13 d9 pci_ad9 d10 pci_c/be0# d11 pci_ad4 d12 pci_req64# d13 pci_c/be5# d14 pci_ad60 d15 pci_ad58 d16 pci_ad55 e1 pci_ad29 e2 vss e3 pci_ad26 e4 pci_idsel e5 vdd33 e6 vdd10 e7 vdd33 e8 vdd10 e9 vdd10 e10 vdd33 table 2-10. ball assignments by location (cont.) location signal name
january, 2007 ball assignments by location expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 31 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 e11 vdd10 e12 vdd33 e13 pci_ad56 e14 pci_ad54 e15 pci_ad53 e16 pci_ad51 f1 pci_ad31 f2 vdd33 f3 pci_ad30 f4 pci_ad28 f5 vdd10 f6 vss f7 vss f8 vss f9 vss f10 vss f11 vss f12 vdd10 f13 pci_ad52 f14 pci_ad50 f15 vss f16 pci_ad49 g1 pci_req1# g2 pci_req# or pci_req0# g3 pci_gnt# or pci_gnt0# g4 pci_pme# g5 vdd10 g6 vss g7 vss g8 vss g9 vss g10 vss g11 vss g12 vdd10 g13 pci_ad48 g14 pci_ad46 g15 vdd33 g16 pci_ad47 table 2-10. ball assignments by location (cont.) location signal name
signal ball description plx technology, inc. 32 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 h1 pci_req3# h2 pci_req2# h3 pci_gnt1# h4 pci_rst# h5 vdd33 h6 vss h7 vss h8 vss h9 vss h10 vss h11 vss h12 vdd33 h13 pci_ad44 h14 pci_ad42 h15 pci_ad45 h16 pci_ad43 j1 pci_clk j2 vdd33 j3 pci_gnt3# j4 pci_gnt2# j5 vdd10 j6 vss j7 vss j8 vss j9 vss j10 vss j11 vss j12 vdd10 j13 pci_ad40 j14 pci_ad38 j15 pci_ad41 j16 pci_ad39 k1 pci_clko1 k2 vss k3 pci_clko0 k4 pci_intc# k5 vdd10 k6 vss table 2-10. ball assignments by location (cont.) location signal name
january, 2007 ball assignments by location expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 33 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 k7 vss k8 vss k9 vss k10 vss k11 vss k12 vdd10 k13 pci_ad36 k14 pci_ad34 k15 pci_ad37 k16 pci_ad35 l1 pci_clko3 l2 pci_clko2 l3 pci_inta# l4 strap_clk_mst l5 strap_arb l6 vss l7 vss l8 vss l9 vss l10 vss l11 vss l12 vdd33 l13 ee_pr# l14 pci_ad32 l15 vss l16 pci_ad33 m1 pci_intb# m2 pci_intd# m3 vdd33 m4 pci_sel100 m5 pex_pern0 m6 vdd10 m7 pex_pern1 m8 vdd10a m9 pex_pern2 m10 vdd10 m11 pex_pern3 m12 vdd10 table 2-10. ball assignments by location (cont.) location signal name
signal ball description plx technology, inc. 34 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 m13 hp_pwrled# m14 ee_sk m15 vdd33 m16 ee_di n1 jtag_tdo n2 jtag_tdi n3 pci_clko_dly_fbk n4 vssa n5 pex_perp0 n6 strap_ext_clk_sel n7 pex_perp1 n8 vss n9 pex_perp2 n10 vss n11 pex_perp3 n12 vss n13 hp_pwrflt# n14 hp_pwren# n15 ee_cs# n16 ee_do p1 jtag_tck p2 jtag_tms p3 strap_pll_bypass# p4 vdd33a p5 vss p6 vss p7 vss p8 vdd10s p9 vss p10 vss p11 vss p12 vdd33 p13 hp_prsnt# p14 hp_perst# p15 strap_tran p16 strap_fwd r1 jtag_trst# r2 strap_te stmode0 table 2-10. ball assignments by location (cont.) location signal name
january, 2007 ball assignments by location expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 35 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 r3 pex_refclkn r4 vdd10s r5 pex_petp0 r6 vdd10s r7 pex_petp1 r8 vdd10s r9 pex_petp2 r10 vdd10s r11 pex_petp3 r12 vdd10s r13 hp_mrl# r14 hp_clken# r15 pex_lane_good1# r16 pex_lane_good3# t1 pex_perst# t2 strap_testmode1 t3 pex_refclkp t4 vss t5 pex_petn0 t6 vtt_pex0 t7 pex_petn1 t8 vss t9 pex_petn2 t10 vtt_pex1 t11 pex_petn3 t12 vss t13 hp_button# t14 hp_atnled# t15 pex_lane_good0# t16 pex_lane_good2# table 2-10. ball assignments by location (cont.) location signal name
signal ball description plx technology, inc. 36 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.11 ball assignments by signal name table 2-11. ball assignments by signal name location signal name n15 ee_cs# m16 ee_di n16 ee_do l13 ee_pr# m14 ee_sk t14 hp_atnled# t13 hp_button# r14 hp_clken# r13 hp_mrl# p14 hp_perst# p13 hp_prsnt# n14 hp_pwren# n13 hp_pwrflt# m13 hp_pwrled# p1 jtag_tck n2 jtag_tdi n1 jtag_tdo p2 jtag_tms r1 jtag_trst# a13 pci_ack64# c12 pci_ad0 a12 pci_ad1 c11 pci_ad2 a11 pci_ad3 d11 pci_ad4 b11 pci_ad5 c10 pci_ad6 a10 pci_ad7 b10 pci_ad8 d9 pci_ad9 a9 pci_ad10 c8 pci_ad11 a8 pci_ad12 d8 pci_ad13 a7 pci_ad14 c7 pci_ad15
january, 2007 ball assignments by signal name expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 37 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 c4 pci_ad16 b3 pci_ad17 d4 pci_ad18 a2 pci_ad19 c3 pci_ad20 a1 pci_ad21 c2 pci_ad22 b1 pci_ad23 d3 pci_ad24 d2 pci_ad25 e3 pci_ad26 d1 pci_ad27 f4 pci_ad28 e1 pci_ad29 f3 pci_ad30 f1 pci_ad31 l14 pci_ad32 l16 pci_ad33 k14 pci_ad34 k16 pci_ad35 k13 pci_ad36 k15 pci_ad37 j14 pci_ad38 j16 pci_ad39 j13 pci_ad40 j15 pci_ad41 h14 pci_ad42 h16 pci_ad43 h13 pci_ad44 h15 pci_ad45 g14 pci_ad46 g16 pci_ad47 g13 pci_ad48 f16 pci_ad49 f14 pci_ad50 e16 pci_ad51 f13 pci_ad52 e15 pci_ad53 table 2-11. ball assignments by signal name (cont.) location signal name
signal ball description plx technology, inc. 38 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 e14 pci_ad54 d16 pci_ad55 e13 pci_ad56 c16 pci_ad57 d15 pci_ad58 b16 pci_ad59 d14 pci_ad60 a16 pci_ad61 c15 pci_ad62 a15 pci_ad63 d10 pci_c/be0# b7 pci_c/be1# a3 pci_c/be2# c1 pci_c/be3# b14 pci_c/be4# d13 pci_c/be5# a14 pci_c/be6# c13 pci_c/be7# j1 pci_clk k3 pci_clko0 k1 pci_clko1 l2 pci_clko2 l1 pci_clko3 n3 pci_clko_dly_fbk a4 pci_devsel# d5 pci_frame# g3 pci_gnt# or pci_gnt0# h3 pci_gnt1# j4 pci_gnt2# j3 pci_gnt3# e4 pci_idsel l3 pci_inta# m1 pci_intb# k4 pci_intc# m2 pci_intd# b4 pci_irdy# b9 pci_m66en d7 pci_par table 2-11. ball assignments by signal name (cont.) location signal name
january, 2007 ball assignments by signal name expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 39 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 c14 pci_par64 a5 pci_pcixcap c5 pci_pcixcap_pu b6 pci_perr# g4 pci_pme# g2 pci_req# or pci_req0# g1 pci_req1# h2 pci_req2# h1 pci_req3# d12 pci_req64# h4 pci_rst# m4 pci_sel100 a6 pci_serr# c6 pci_stop# d6 pci_trdy# t15 pex_lane_good0# r15 pex_lane_good1# t16 pex_lane_good2# r16 pex_lane_good3# m5 pex_pern0 m7 pex_pern1 m9 pex_pern2 m11 pex_pern3 n5 pex_perp0 n7 pex_perp1 n9 pex_perp2 n11 pex_perp3 t1 pex_perst# t5 pex_petn0 t7 pex_petn1 t9 pex_petn2 t11 pex_petn3 r5 pex_petp0 r7 pex_petp1 r9 pex_petp2 r11 pex_petp3 r3 pex_refclkn t3 pex_refclkp table 2-11. ball assignments by signal name (cont.) location signal name
signal ball description plx technology, inc. 40 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 l5 strap_arb l4 strap_clk_mst n6 strap_ext_clk_sel p16 strap_fwd p3 strap_pll_bypass# r2 strap_testmode0 t2 strap_testmode1 p15 strap_tran e6 vdd10 e8 vdd10 e9 vdd10 e11 vdd10 f5 vdd10 f12 vdd10 g5 vdd10 g12 vdd10 j5 vdd10 j12 vdd10 k5 vdd10 k12 vdd10 m6 vdd10 m10 vdd10 m12 vdd10 m8 vdd10a p8 vdd10s r4 vdd10s r6 vdd10s r8 vdd10s r10 vdd10s r12 vdd10s b2 vdd33 b8 vdd33 b12 vdd33 b15 vdd33 e5 vdd33 e7 vdd33 e10 vdd33 e12 vdd33 table 2-11. ball assignments by signal name (cont.) location signal name
january, 2007 ball assignments by signal name expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 41 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 f2 vdd33 g15 vdd33 h5 vdd33 h12 vdd33 j2 vdd33 l12 vdd33 m3 vdd33 m15 vdd33 p12 vdd33 p4 vdd33a b5 vss b13 vss c9 vss e2 vss f6 vss f7 vss f8 vss f9 vss f10 vss f11 vss f15 vss g6 vss g7 vss g8 vss g9 vss g10 vss g11 vss h6 vss h7 vss h8 vss h9 vss h10 vss h11 vss j6 vss j7 vss j8 vss j9 vss j10 vss table 2-11. ball assignments by signal name (cont.) location signal name
signal ball description plx technology, inc. 42 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 j11 vss k2 vss k6 vss k7 vss k8 vss k9 vss k10 vss k11 vss l6 vss l7 vss l8 vss l9 vss l10 vss l11 vss l15 vss n8 vss n10 vss n12 vss p5 vss p6 vss p7 vss p9 vss p10 vss p11 vss t4 vss t8 vss t12 vss n4 vssa t6 vtt_pex0 t10 vtt_pex1 table 2-11. ball assignments by signal name (cont.) location signal name
january, 2007 physical ball assignment expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 43 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 2.12 physical ball assignment figure 2-1. pex 8114 256-ball pbga package physical ball assignment (underside view) 16 15 14 1 3 12 11 10 9 8 7654 3 21 a pci_ad61 pci_ad63 pci_c/be6# pci_ack64# pci_ad1 pci_ad3 pci_ad7 pci_ad10 pci_ad12 pci_ad14 pci_serr# pci_pcixcap pci_devsel# pci_c/be2# pci_a d19 pci_ad21 a b pci_ad5 9 vdd33 pci_c/be4# v ss vdd33 pci_ad5 pci_ad 8 pci_m66en vdd33 pci_c/be1# pci_perr# v ss pci_irdy# pci_ad17 vdd33 pci_ad23 b c pci_ad57 pci_ad62 pci_par64 pci_c/be7# pci_ad0 pci_ad2 pci_ad6 v ss pci_ad11 pci_ad15 pci_stop# pci_pcixcap _pu pci_ad16 pci_ad20 pci_ad22 pci_c/be3# c d pci_ad55 pci_ad58 pci_ad60 pci_c/be5# pci_req64# pci_ad4 pci_c/be0# pci_ad 9 pci_ad13 pci_par pci_trdy# pci_frame# pci_ad1 8 pci_ad24 pci_ad25 pci_ad27 d e pci_ad51 pci_ad53 pci_ad54 pci_ad56 vdd33 vdd10 vdd33 vdd10 vdd10 vdd33 vdd10 vdd33 pci_idsel pci_ad26 v ss pci_ad29 e f pci_ad49 v ss pci_ad50 pci_ad52 vdd10 v ss v ss v ss v ss v ss v ss vdd10 pci_ad2 8 pci_ad 3 0 vdd33 pci_ad 3 1 f g pci_ad47 vdd33 pci_ad46 pci_ad4 8 vdd10 v ss v ss v ss v ss v ss v ss vdd10 pci_pme# pci_gnt# or pci_gnt0# pci_req# or pci_req0# pci_req1# g h pci_ad4 3 pci_ad45 pci_ad42 pci_ad44 vdd33 v ss v ss v ss v ss v ss v ss vdd33 pci_r s t# pci_gnt1# pci_req2# pci_req 3 # h j pci_ad 39 pci_ad41 pci_ad 38 pci_ad40 vdd10 v ss v ss v ss v ss v ss v ss vdd10 pci_gnt2# pci_gnt 3 # vdd33 pci_clk j k pci_ad 3 5 pci_ad 3 7 pci_ad 3 4 pci_ad 3 6 vdd10 v ss v ss v ss v ss v ss v ss vdd10 pci_intc# pci_clko0 v ss pci_clko1 k l pci_ad 33 v ss pci_ad 3 2 ee_pr# vdd33 v ss v ss v ss v ss v ss v ss s trap_arb s trap_clk_ m s t pci_inta# pci_clko2 pci_clko 3 l m ee_di vdd33 ee_ s k hp_pwrled# vdd10 pex_pern 3 vdd10 pex_pern2 vdd10a pex_pern1 vdd10 pex_pern0 pci_ s el100 vdd33 pci_intd# pci_intb# m n ee_do ee_c s # hp_pwren# hp_pwrflt# v ss pex_perp 3 v ss pex_perp2 v ss pex_perp1 s trap_ext_ clk_ s el pex_perp0 v ss a pci_clko_dl y_fbk jtag_tdi jtag_tdo n p s trap_fwd s trap_tran hp_per s t# hp_pr s nt# vdd33 v ss v ss v ss vdd10 s v ss v ss v ss vdd 33 a s trap_pll_b ypa ss # jtag_tm s jtag_tck p r pex_lane_g ood 3 # pex_lane_g ood1# hp_clken# hp_mrl# vdd10 s pex_petp 3 vdd10 s pex_petp2 vdd10 s pex_petp1 vdd10 s pex_petp0 vdd10 s pex_refclkn s trap_te s t mode0 jtag_tr s t# r t pex_lane_g ood2# pex_lane_g ood0# hp_atnled# hp_button# v ss pex_petn 3 vtt_pex1 pex_petn2 v ss pex_petn1 vtt_pex0 pex_petn0 v ss pex_refclkp s trap_te s t mode1 pex_per s t# t 16 15 14 1 3 12 11 10 9 8 7654 3 21
signal ball description plx technology, inc. 44 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 45 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 3 clock and reset 3.1 pex 8114 clocking introduction note: the pex 8114 is compliant with the pci-x addendum to pci local bus specification, revisions 1.0b and 2.0a. the pci/pci-x clock domain pll is driven by the 100-mhz pex_refclkn/p input, as well as pci_clk input. when the pci/pci-x clock domain pll is driven by pex_refclkn/p, the pll is used to synthesize the pci system clock and is referred to as operating in clock master mode . when the pci/pci-x clock domain pll is driven by pci_clk, it is referred to as operating in clock slave mode . the pex 8114 includes a pci-x bus clock generato r and two internal clock domains ? one each for pci-x and pci express. the clock generator is capable of synthesizi ng common pci clock frequencies and driving four clock output balls, pci_clko[3:0] . the pci express clock domain runs at a frequency that is compatible with 2.5 gbps pc i express data transmission rates, and is a slave to the pex_refclkn/p inputs. the pci-x clock domain is driven by the pci_clk input system clock, and runs at the pci-x bus clock frequency. 3.1.1 pci-x clock generator the pex 8114 pci/pci-x (pci-x) clock generator is used to synthesize pci-x bus clocks. the pci-x clock generator is driven by pex_refclkn/p, and can generate four externally usable pci-x bus system clocks. these clocks are driven out of the pex 8114 onto the pci_clko[3:0] balls. pci_clko[3:0] are designed to dr ive four external pci devices. in addition to pci_clko[3:0], the clock master circuitry also provides a pci_clko_dly_fbk clock output ball. the pci_clko_dly_fbk output can optionally drive the pci_clk input to the pex 8114, by way of a trace on the printed circui t board (pcb). this ensure s that the pci-x system clock-phase alignment requirements are satisfied when other devices are located requiring long clock lines on the pcb. the pci/pci-x clock generator is enabled when the strap_clk_mst input ball is high. the synthesized pci/pci-x clock fr equency is determined by the pci_m66en , pci_pcixcap , pci_pcixcap_pu , and pci_sel100 balls. (refer to section 3.3 .) the clock generator is capable of synthesizing frequencies at 25. 33. 50, 66, 100, and 133 mhz. when the clock generator is disabled, the pci_clko[3:0] and pci_clko_dly_fbk signals are driven low. additionally, the pci_clko[3:0] signals can be individually disa bled by writing 0 to th e register bit associated with that specific output (offset fa0h , pci_clko_en[3:0] field). when the pex 8114 exits reset with strap_clk_mst low, the pci_clko[3:0] and pci_clko_dly_fbk outputs are driven low. when strap_clk_mst is high at pex 8114 reset, the pci_clko[3:0] and pci_clko_dly_fbk outputs drive active clocks. when the pex 8114 is the clock master, it sets the mode (pci or pci-x) and the clock frequency when reset de-asserts.
clock and reset plx technology, inc. 46 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.1.2 pci-x clocking of pci-x module the pex 8114 pci-x module must be supplied a cloc k from the pex 8114?s internal clock generator or a system-level clock generator. the pci clocks , at the input ball of each device on the pci bus segment, must be frequency- and phase-aligned. 3.1.2.1 clocking the pci module when pex 8114 clock generator is not used when the pex 8114 is not used as the pci system clock generator, the pex 8114 receives the pci bus system clock from its pci_clk input signal. the external clock generator is required to supply the clocks to the various pci devices, allowing the devices to meet the phase-alignment requirements. the pci-x module can be driven at pci-x clock fr equencies up to 133 mhz, as well as pci clock frequencies down to dc. the pci-x module determines to which mode (pci or pci-x) and frequency it is be driven at reset, by reading the initialization pattern on the pci bus, as described in the pci-x r1.0b and pci-x r2.0a . 3.1.2.2 clocking the pci module w hen pex 8114 clock generator is used when the pex 8114?s clock generation circuitry is used (by setting strap_clk_mst =1), the pci clock can be driven to the pci circuitr y, internally or externally across the pcb: when the pci clock must be internally driven from the pex 8114?s clock generator to the pex 8114 pci device, drive the strap_ext_clk_sel ball low. when the pci clock must be externally driv en on the pcb, run a clock trace from the pex 8114?s pci_clko_dly_fbk output to the pci_clk input, then drive the strap_ext_clk_sel ball high. the ability to drive an external pci_clk pcb trace back to the pci express interface allows for delay, an d the ability to align the pex 8114?s pci_clk input with the other device?s pci_clk inputs, alt hough the other device?s cl ocks are driven across a long pcb trace. typically, the pcb trace lengt h from the pci_clko_dly _fbk output to the pci_clk input is equal to the length of the clock traces from the pex 8114?s pci_clko[3:0] balls to the other external device?s clock inputs.
january, 2007 determining pci bus and internal clock initialization expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 47 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.2 determining pci bus and internal clock initialization the strap_fwd and strap_clk_mst strapping ball s are used to configure the pex 8114 as a forward or reverse transparent bridge and as a clock slave or master. the pex 8114 is capable of operating as a forward or reverse pci express bridge, using its internal pll to synthesize a pci clock for the pci bus, or it can become a slave to an incoming pci clock: pci mode ? pex 8114 is capable of op erating as a clock master at 25, 33, 50, or 66 mhz, or clock slave, at frequencies from 66 mhz down to dc pci-x mode ? pex 8114 is capable of operating as a clock master at 50, 66, 100, or 133 mhz, or clock slave, at frequencies from 133 mhz down to dc to determine configuration of its internal resources and the pci bus when appropriate (because it is assuming the role of a central resource that perfor ms bus initialization), the pex 8114 can read the maximum bus capability and ini tialize the pci bus, accordingly. this section defines actions the pex 8114 takes to perform the following: 1. determine the pci bus maximum capability. 2. initialize its internal pci pll to clock master or slave configuration. 3. drive the initialization pattern at pci_rst# de-assertion. 4. drive or receive the pci_rst# signal. table 3-1 defines the pex 8114 operation when configured to run as a forward or reverse pci express bridge, as a clock master or slave. table 3-1. pex 8114 pci clock configurations and functions mode bus capability internal clock configuration bus initialization pattern pci_rst# forward transparent bridge as pci clock master detects synthesize pci clock and pci_clko[3:0] balls drive drive forward transparent bridge as pci clock slave slave to pci clock reverse transparent bridge as pci clock master detects synthesize pci clock and pci_clko[3:0] balls drive receive reverse transparent bridge as pci clock slave does not detect slave to pci clock receive
clock and reset plx technology, inc. 48 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.2.1 determining bus mode ca pability and maximum frequency the pex 8114, as a clock master or forward pci express bridge in clock slave mode, must determine the system?s bus mode capabilities and maximum frequency, using the pci_pcixcap and pci_pcixcap_pu balls. table 3-2 defines the maximum clock frequency and pci_pcixcap ball circuitry. for the three clock frequencies listed in the table, connect the pci_pcixcap_pu ball to the pci_pcixcap ball through a 1k-ohm resistor. a 56k-ohm resistor between 3.3v and the pci_pcixcap ball is also required. the pex 8114 detects this circuitry to determine the bus mode and maximum clock frequency, at power-up. table 3-2. bus mode, maximum clock frequency, and pci_pcixcap ball circuitry bus mode maximum clock frequency pci_pcixcap ball pci 66 mhz grounded pci-x 66 mhz grounded through an rc network 133 mhz connected to a capacitor
january, 2007 pci clock master mode expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 49 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.3 pci clock master mode when the pex 8114 is strapped as the clock ma ster (strap_clk_mst=1), the pex 8114 uses the 100 mhz reference clock ( pex_refclkn/p ) to synthesize the pci_clko clock(s). it determines the frequency to synthesize by sampling the pci_m66en , pci_pcixcap , and pci_sel100 balls (refer to table 3-3 ) during the clock initialization period. the clock initialization period is the time following pci express power good reset input ( pex_perst# ) de-assertion, prior to pci reset ( pci_rst# ) de-assertion. during the clock initialization period, the pex 811 4 runs a simple state m achine to determine the frequency generated by the clock synthesizer. the state machine samples the pci_m66en, pci_pcixcap, and pci_sel100 balls to determine th e correct pci_clko frequency, initializes the clock synthesizer, drives the correct bus initialization values on the pci_devsel# , pci_stop# , and pci_trdy# signals and, when the pll locks, de-asse rts pci_rst# (forward transparent bridge mode) or waits for pci_rst# de-assertio n (reverse transparent bridge mode). when strap_fwd =1 (forward transparent bridge mode ), the pex 8114 drives pci_rst# and asserts pci_rst# during the initialization period. when strap_fwd=0 (reverse transparent bridge mode), pci_rst# is an input. the pex 8114 drives initialization values on the pci_devsel#, pci_stop#, and pci_trdy# balls during the initialization period. in this configuration, the pex 8114 requires external logic to drive pci_rst#. table 3-3 defines the pll divider frequency. figure 3-1 through figure 3-3 illustrate the pertinent signals and the clock initializati on and reset sequence that the pex 8114 follows when strapped in clock master mode. note: ?x? indicates ?don?t care.? table 3-3. clock master mode pll divider frequency mode clock frequency pci_pcixcap pci_sel100 pci_m66en pci 25 mhz gnd 1 0 33 mhz 0 50 mhz 1 1 66 mhz 0 pci-x 50 mhz 10k to gnd 1 x 66 mhz 0 100 mhz high 1 133 mhz 0
clock and reset plx technology, inc. 50 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.3.1 clock master mode signals figure 3-1 illustrates the clock signal for clock master mode. figure 3-1. clock signal for clock master mode notes: 1. pll is driven by the 100-mhz pex_refclkn/p . 2. pll is used to gene rate 25, 33, 50, or 66 (pci), or 66, 100, or 133 (pci-x) mhz. 3. pci_clko[3:0] frequency is synthesized from the 100-mhz signal. 4. pci_clko[3:0] must drive the pci bus, and pci_clk is unused, unless the pex 8114 is configured in clock feedb ack mode by strapping strap_ext_clk_sel input high. 5. strap_clk_mst=1. figure 3-2 illustrates the pex 8114 config ured as a clock master in fo rward transparent bridge mode. this configuration uses the 100 mhz reference clock ( pex_refclkn /p) to generate 25-, 33-, 50-, 66-, 100-, or 133-mhz pci_clko[3:0] signals and a phas e-advanced internal clock. the diagram notes explain the clock?s functions and limitations. pci_rst# is an output in forward transparent bridge mode. figure 3-2. clock master mode ? forward transparent bridge mode step 1 pex_perst# is de-asserted, a nd strap_clk_mst and strap_fwd are high. step 2 pex 8114 reads pci_pcixcap , pci_m66en , and pci_sel100 to determine clock frequency. step 3 pex 8114 loads its internal pll values. step 4 pex 8114 internal pll reports lock up. step 5 pex 8114 drives pci_devsel# , pci_stop# , and pci_trdy# initial values. step 6 pex 8114 de-asserts pci_rst# . 100 mhz ref pci_clko[3:0] = f (100 mhz) pci_clko[3:0] pci_clko3 pci_devsel# pci_rst# pci_clko2 pci_clko1 pci_clko0 pci_stop# pci_trdy# pci_pcixcap_pu clock master / forward transparent bridge mode inputs outputs strap_fwd = 1 strap_clk_mst = 1 pex_refclkn/p pex_perst# pci_pcixcap pci_m66en pci_sel100
january, 2007 clock master mode signals expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 51 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 figure 3-3 illustrates the clock master in reverse tr ansparent bridge mode. reverse transparent bridge mode differs from forward transparent bridge mode, in that the strap_fwd input ball is strapped low and pci_rst# becomes an input in reverse clock master mode. figure 3-3. clock master mode ? reverse transparent bridge mode step 1 pex_perst# is de-asserted, strap_ clk_mst is high, and strap_fwd is low. step 2 pex 8114 reads pci_pcixcap , pci_m66en , and pci_sel100 to determine clock frequency. step 3 pex 8114 loads its internal pll values. step 4 pex 8114 pll reports lock up internally. step 5 pex 8114 drives pci_devsel# , pci_stop# , and pci_trdy# initial values. step 6 pci_rst# is de-asserted by external (system) logic. the external system logic must allow pci_rst# to remain low for 1 ms. trst, as required by the pci r3.0 . internal plls lock up during this 1 ms period. pex_perst# pci_pcixcap pci_m66en pci_clko3 pci_devsel# pci_rst# pci_clko2 pci_clko1 pci_clko0 pci_stop# pci_trdy# pci_pcixcap_pu clock master / reverse transparent bridge mode inputs outputs strap_fwd = 0 pex_refclkn/p strap_clk_mst = 1 pci_sel100
clock and reset plx technology, inc. 52 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.4 pci clock slave mode when the pex 8114 is strapped as a clock slave ( strap_clk_mst =0), a pll is used to cancel the internal clock fan-out delay for pci clock frequencies above 33 mhz. when a pci_clk frequency is 33 mhz or lower, the pll is bypassed and pci_cl k directly drives the pci internal circuitry. 3.4.1 clock slave ? forward transparent bridge mode when the clock slave state machine is run in forw ard transparent bridge mode, the pex 8114 receives a clock, but takes responsibility to drive the pci-x initia lization pattern at rese t. because the pex 8114 drives the initialization pattern, it detects the circuit connected to the pci_pcixcap , pci_m66en , and pci_sel100 ball states to determine the pci bus maximum clock frequency and which pci-x initialization pattern to drive. external clock generation circuitry must: determine and set the clock frequency, accordi ng to the values on pc i_pcixcap, pci_m66en, and pci_sel100, or limit the system maximum clock frequency by driving values on pci_pcixcap, pci_m66en, and pci_sel100 this requires coordination of the clock generator frequency and the values that the pex 8114 reads on the pci_pcixcap, pci_m66en, and pci_sel100 balls.
january, 2007 clock slave ? forward transparent bridge mode expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 53 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 figure 3-4 illustrates the pertinent signals and re set sequence that the pex 8114 follows when strapped in clock slave mode. the pex 8114 supplies the bus initialization in forward transparent bridge mode. figure 3-4. clock slave mode ? forward transparent bridge mode step 1 pex_perst# is de-asserted, strap_ clk_mst is low, and strap_fwd is high. step 2 pex 8114 reads pci_pcixcap , pci_m66en , and pci_sel100 to determine clock frequency at which pci_clk is driven into pex 8114 by an external clock generator. step 3 pex 8114 sets up to use its intern al pll and waits until lock if the clock frequency is greater than 33 mhz. if the clock frequency is 33 mhz or lowe r, the internal pll is bypassed. step 4 pex 8114 drives pci_devsel# , pci_stop# , and pci_trdy# during the initialization period prior to de-asserting pci_rst# . an external source provides pci_clk. clock slave / forward transparent bridge mode strap_clk_mst = 0 pci_clk pci_rst# pci_m66en pci_sel100 pci_stop# pci_trdy# pex_perst# inputs outputs pci_devsel# pci_pcixcap strap_fwd = 1
clock and reset plx technology, inc. 54 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.4.2 clock slave ? reverse transparent bridge mode the pex 8114 in reverse clock slave mode , reads the initialization pattern at pci_rst# de-assertion, to determine bus mode and clock freq uency, then loads the internal pll. when the pex 8114 is a reverse clock slave, it is not the central resource and as such, it must detect the pci-x initialization pattern to determine protocol and frequency. for this mode, pci_pcixcap , pci_pcixcap_pu , and pci_sel100 can be pulled high or low. figure 3-5. clock slave mode ? reverse transparent bridge mode step 1 pex_perst# is de-asserted, and strap_clk_mst and strap_fwd are low. step 2 pex 8114 waits for pci_rst# de-assertion and the initialization pattern (driven by a device other than pex 8114). step 3 system pci clock rate is indicated to the pex 8114 by the initializati on pattern at pci_rst# de-assertion. if the pci clock rate indicated by the initialization pattern is 33 mhz, bypass the internal pll. if the initialization pattern indicates a clock rate greater than 33 mhz, load the internal pll with appropriate settings. clock slave / reverse transparent bridge mode strap_fwd = 0 inputs pci_clk pci_stop# strap_clk_mst = 0 pex_perst# pci_rst# pex_devsel# pci_trdy#
january, 2007 timing diagrams ? forward or reverse transparent bridge mode expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 55 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.4.3 timing diagrams ? forward or reverse transparent bridge mode figure 3-6. phase offset in clock slave mode ? frequency > 33 mhz notes: 1. pll is driven by the pci_clk input. 2. the pll input and output frequencies are equal to one another. the pll is used to provide phase advance to compensate for clock tree delay within the pex 8114. 3. pclk is equal to the pci_clk input, in frequency and phase. 4. strap_clk_mst =0 figure 3-7. phase offset in clock slave mode ? frequencies < 33 mhz notes: 1. pll is bypassed. this is applicable to clock slave mode at pci clock rates < 33 mhz. 2. the internal pclk is phase-delayed with respect to the pci_clk input. 3. pci_clk must drive the pci/pci-x bus and pex 8114. do not use pci_clko[3:0] to drive the pci/pci-x bus pci_clk traces. 4. strap_clk_mst=0. pci_clk pclk phase pclk pci_clk phase
clock and reset plx technology, inc. 56 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 the pci express and pci-x plls contain a signal th at indicates to the pex 8 114 whether the pll lost the pll lock. it is considered a serious error co ndition if the pci express or pci-x pll, when the pci-x pll is in phase-locked mode ( that is , when not in pll bypass mode ), indicates a loss of pll lock and potential data errors. loss of pll lock can be caused by one of the following: serious out-of-specification noise voltages on the pll power inputs out-of-specification jitter on the input reference clocks table 3-4 defines the options for handling loss of pll lock. the options are selected by the pll lock control 1 and pll lock control 0 bits (offset fa0h [11:10]). by default, this field is cleared to 00b, which configures the pex 8114 to ignore loss of pll lock. sticky bits are set when the pci ex press or pci-x pll loses pll lock: when the pci express pll loses pll lock, the sticky pci express pll loss lock bit is set (offset fa0h [15]=1) when the pci-x pll loses pll lock, the sticky pci-x pll loss lock bit is set (offset fa0h [14]=1) table 3-4. methods for handling loss of pll lock offset fa0h[11:10] description 00b default. ignores loss of pll lock. 01b loss of pll lock immediatel y causes the pex 8114 to reset. 10b the pex 8114 attempts to to lerate loss of pll lock: when lock is re-acquired in less than 200 s, the pex 8114 is not reset when lock is not re-acquired with in 200 s, the pex 8114 is reset 11b the pex 8114 is not reset if loss of pll lock occurs.
january, 2007 resets expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 57 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5 resets this section explains the pex 8114 reset mechan ism and how the differences between pci express and pci-x resets are incorporated in forwar d and reverse transparent bridge modes. the pci express r1.0a and pci-x r1.0b define two common levels or reset types, level-1 and level-2. the pci express r1.0a defines an additional third level, level-0. table 3-5 defines resets. table 3-5. reset table reset type pci express definition reset source impact to various internal components (upon de-assertion) impact to internal registers (no aux and pme enabled) level-0 fundamental reset cold reset warm reset pex_perst# reset input assertion initialize entire bridge, including sticky registers serial eeprom contents are loaded hwinit types evaluated all registers initialized level-1 forward transparent bridge mode: hot reset reset bit of the ts ordered-set is set, at upstream port upstream port entering dl_down state initialize ports initialize entire bridge except the sticky registers serial eeprom contents re-loaded (selectively) all registers initialized, with following exceptions: port configuration registers all sticky bits not affected by hot reset (hwinit, r/ws, r/w1cs, ros) reverse transparent bridge mode: pci_rst# pci_rst# is asserted on pci/pci-x bus level-2 secondary bus reset forward transparent bridge mode assert pci_rst# on pci-x bus drain traffic drop request tlps redefine bus mode and clock frequency in clock master mode no effect to csrs reverse transparent bridge mode pci express pl propagates hot reset pci express dll down tlp layer initialized and exhibits dl_down behavior drops request tlps drain traffic corresponding to dl_down behavior and initialize credits redefine bus mode and clock frequency in clock master mode no effect to csrs (other than to initialize credits)
clock and reset plx technology, inc. 58 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5.1 level-0, fundamental reset (power-on, hard, cold, warm) the pci express r1.0a defines the fundamental reset or level-0 reset . level-0 reset is a fundamental reset. it is equivalent to traditional power-on reset. for this type of reset, pex_perst# is always an input to the pex 8114 , regardless of whether the bridge is operating in forward or reverse transparent bridge mode . reset assertion by the system, external to the pex 8114, causes a reset of all inte rnal pex 8114 registers, including sticky bits, and drives all state machines to known states. 3.5.1.1 pex_perst# in pci express, fundamental reset can be provid ed by the system host or central resource. the sideband pci express reset signal (pex_perst#) is routed in parallel to all system pci express devices in conjunction with a power good signal from the system power supply. for the pex 8114, the pex_perst# signal is always an input in forw ard and reverse transparent bridge modes, which indicates that the power is within specified toleran ces and that the pex 8114 performs internal warm or cold reset. in forward transparent bridge mode, the pci expr ess root complex feeds the pex_perst# signal to all devices. pex_perst# is driven in parallel to all pci express devices, following the pci express power good reset standard practice. in reverse transparent bridge mode, the pci central resource, including power supply monitors, feeds the pex_perst# signal to all pci express devices. th e mechanism traditionally used to reset pci bus segments is preserved in reverse transparent bridge mode, by transmitting protocol hot resets to reset bridges and bus segments. when the pex 8114 is operating in reverse tran sparent bridge mode, th e pex_perst# signal is expected to function similar to the pwr_good signal in the pci r3.0 , figure 4.11, and to follow the timing and functionality defined in the pci r3.0 , section 4.3.2.
january, 2007 level-0, fundamental reset (power-on, hard, cold, warm) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 59 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5.1.2 level-0 reset ? forwa rd transparent bridge mode in forward transparent bridge mode, when the system asserts pex_perst# to the pex 8114, pci_rst# is asserted on the pci/pci-x bus. figure 3-8 illustrates the timing relationship between pex_perst#, pci_rst#, and the pex 8114 internal reset in forward transparent bridge mode. figure 3-8. pex_perst# input, pci_rst# output, and intern al reset timing in forward transparent bridge mode timing requirement the pci r3.0 places a power-up timing requirement on the pci_rst# bus reset signal ( that is , pci_rst# must remain asserted for 1 ms after powe r becomes stable). this applies to the pex 8114 in forward transparent bridge mode because th e pex 8114 asserts pci_rst# in this mode. when power is first applied, pex_perst# is assert ed by the central resource and remains asserted until power is stable. pci_rst# is asserted for 1 ms after pex_perst# de-assert ion, to guarantee that pci_rst# is asserted for 1 ms after power stabilizes. manual switches ? defining a warm reset in forward transparent bridge mode the pci express reset, from the pex_perst# input ball, is a level-0 reset asserted on power-up until board power stabilizes. on-board manual switches for hard resets to the pex 8114 also control pex_perst# when an on-board reset switch or similar mechanism is used to assert reset by way of pex_perst# without cycling the power supply (warm reset). note: perform warm resets only in forward transparent bridge mode. pex_perst# internal reset pci_rst# 1 ms
clock and reset plx technology, inc. 60 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5.1.3 level-0 reset ? reverse transparent bridge mode in reverse transparent bridge mode, pci_rst# is an input. the pex 8114 requires that pci_rst# be asserted during pex_perst# assertion and for an additional 1 ms after pex_perst# de-assertion. figure 3-9 illustrates the pex_perst# and pci_rst# timing waveforms during fundamental reset in reverse transparent bridge mode. figure 3-9. pex_perst# and pci_rst# timi ng in reverse transparent bridge mode timing requirement in reverse transparent bridge mode, after powe r-on, pex_perst# (by the central resource) and pci_rst# (by the upstream bridge) are asserted. pex_perst# and pci_rst# must remain asserted until power becomes stable. when power is stable, pex_perst# must de-assert first and, a minimum of 1 ms later, pci_rst# can de-assert. there is no limit on the maximum pex_perst# assertion time; however, pci_rst# must continue 1 ms longer or the pex 8114 might not function correctly. this requirement is associated with initialization pattern capture. manual switches ? defining a warm reset in reverse transparent bridge mode in reverse transparent bridge mode , when pex_perst# is asserted, pc i_rst# must also be asserted. when pci_rst# is asserted, the initialization pattern is driven on the pci/pci-x bus and the pattern is captured when pci_rs t# is de-asserted. when the pex 8114 is strapped as the clock master in reverse transparent bridge mode, it drives the initialization pattern on the pci/pci-x bus, but not the pex 8114 pci_rst# signal. pex_perst# pci_rst# 1 ms
january, 2007 level-1, hot reset expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 61 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5.2 level-1, hot reset the level-1 reset defined by pci express r1.0a is carried on the pci_rst# ball. this reset level is defined by the pci express r1.0a as an in-band message communicated across a link and is referred to as a hot reset . level-1 reset causes the reset of internal registers and state mach ines, but not register sticky bits. this reset also propagates acro ss the bridge and to the downstream devices. 3.5.2.1 level-1 reset ? forwa rd transparent bridge mode when the pex 8114 is reset during standard operation in forward transparent bridge mode, it is achieved by receiving the in-band messaging reset or hot reset. level-1 reset is received by the pex 8114 on the pci express link as an in-band message and propagated downstream, through pci_rst# assertion as an output signal. level-1 reset is propagated to the pex 8114 by way of an in-band reset message through the pci express link, using the physical layer mechanism (the reset bit in the training ordered-set from the upstream device is asserted). in addition to the in-band reset, if the pex 8114 upstream pci express port proceed s to a dl_down state, for any reason, this is also treated as a hot reset or level-1 reset. this reset is propagated downstream from the pex 8114, by asserting a reset on pci_rst#. pci_rst# is asserted if the in-band hot reset is received by the pci express interface. the pci r3.0 requires that pci_rst# reset, applied during standard operation, must retain a minimum assertion time of 1 ms. in the case of a hot reset, the host software must provide the 1 ms pci_rst# duration, by transmitting the in-band hot reset for 1 ms. figure 3-10 illustrates the timing of propagating pci_rst# when a hot reset is received by the pci express interface. figure 3-10. in-band hot reset, pci_rst#, and internal reset timing in forward transparent bridge mode pci express hot reset pci_rst# 1 ms receiving hot reset messages
clock and reset plx technology, inc. 62 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5.2.2 level-1 reset ? reve rse transparent bridge mode in reverse transparent bridge mode, level-1 reset is received by the pex 8114 on the pci-x interface pci_rst# ball as an input, and propagated downstream as an in-band message on the pci express link (using the physical layer mechanism). level-1 reset is the equivalent to hot reset in forward transparent bridge mode received on the pci express interface. it causes the re set of internal registers and stat e machines, but not register sticky bits. the pci r3.0 requires that pci_rst# be asserted for a minimum of 1 ms. level-1 reset also causes the serial eeprom relo ad, bus mode recheck, and clock frequency recheck. when pci_rst# is asserted, it is propagated acros s the bridge and downstream on the pci express link as a hot reset. during the time that pci_rst# is asserted in-band, hot reset messages are continuously transmitted across the pci express link. figure 3-11 illustrates the timing relationship between pci_rst# and transmitting in-band hot reset messages. figure 3-11. pci_rst# and hot reset message timing in reverse transparent bridge mode 1 ms pci_rst# pci express hot reset sending hot reset messages
january, 2007 secondary bus reset, level-2 reset expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 63 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.5.3 secondary bus reset, level-2 reset level-2 reset is provided by the internal bridge control register secondary bus reset bit (bit 6). this reset drives the bridge state machin es to a known state, but not intern al register resets. this reset also propagates a reset to downstream devices in the same manner as level-1 reset. level-2 resets are sustained until the secondary bus reset bit is cleared. this bit is set and cleared by software, using configuration write accesses. the secondary bus reset is used to reset all downstream devices, without resetting the bridge. 3.5.3.1 level-2 reset ? forwa rd transparent bridge mode level-2 reset, when the secondary bus reset bit is set to 1, is propagated downstream in forward transparent bridge mode, th rough pci_rst# assertion. in forward transparent bridge mode, pci_rst# is a sserted on the pci/pci-x bus when this bit is set. the minimum duration for pci_rst# is 1 ms. the pex 8114 internal state machines are forced to initial states and internal tr ansaction queues are flushed. figure 3-12 illustrates the timing relationship between secondary bus reset and pci_rst# in forward transparent bridge mode. figure 3-12. secondary bus reset and pci_rst# timing in forward transparent bridge mode 3.5.3.2 level-2 reset ? reve rse transparent bridge mode level-2 reset, when the secondary bus reset bit is set to 1, is propagated downstream through an in-band message on the pci express link. when this bit is set in reverse transparent bridge mode, in-band message reset is communicated through the pci express link from the pex 8114 to the downstream devices. the pex 8114 internal state machines are forced to initial states and internal transaction queues are flushed. figure 3-13 illustrates the relationship between the secondary bus reset bit and transmitting in-band hot reset messages. figure 3-13. secondary bus reset and hot reset message timing in reverse transparent bridge mode secondary bus reset pci_rst# 1 ms secondary bus reset hot reset messages sending hot reset messages
clock and reset plx technology, inc. 64 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 3.6 serial eeprom load sequence serial eeprom data is loaded when a level-1 reset is de-asserted. level-1 reset is asserted during the following: power-on reset pex_perst# assertion hot reset (forward transparent bridge mode) pci_rst# assertion (reverse transparent bridge mode) the serial eeprom data is read from the serial ee prom and written into th e configuration registers. this process takes approximately 8,000 pci bus clock cycles. figure 3-14 illustrates the timing of level-1 reset and serial eeprom data loading. when a serial eeprom is pres ent, as indicated by the ee_pr# ball, the serial eeprom controller is triggered to perform a serial eeprom load under the following conditions: upon level-0 reset de-assertion upon level-1 reset de-assertion the purpose of loading from serial eeprom on a le vel-1 reset is to restore registers to customized values, stored in the serial eeprom, after a level-1 (hot) reset initializes registers to default values. consider the typical usage model wherein the seri al eeprom contents are m odified after a level-0 reset. it is possible for a system to change th e serial eeprom contents through the serial eeprom controller after a level-0 reset and restore the values , as modified, with a lo ad upon a level-1 reset. figure 3-14. level-1 reset and loading of seri al eeprom data timing level-1 reset serial eeprom load data is loaded from serial eeprom to configuration registers 8,000 pci bus clock cycles
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 65 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 4 data path 4.1 internal data path description the pex 8114 bridge supports data transfers from the pci-x port to the pci express port. the pci-x port operates in pci or pci-x mode, at clock rates up to 133 mhz and 32- or 64-bit bus widths. the pci express port is four lanes wide and can be configured as a 4-, 2-, or 1-lane port. the pex 8114 internal data path is based on a central ram. which holds and orders all data transferred through the bridge in three separate linked lists including posted, non-posted and completion data. there is a separate, central 8-kb ram for data fl owing in each direction. all transactions are held within the ram in a double store-and-forward method . separate link lists for posted and non-posted transactions, as well as completions, share space within the ram and all link list accesses to the internal ram output are governed, acco rding to pci express ordering rules. at least 2 kb of the 8-kb ram are dedicated to completions. completions can optionally require as much as 6 kb of memory, according to demand. the remainder of th e ram is used for posted and non-posted requests, or remains empty. in addition to the central ram, there ar e eight, 256-byte buffers in the pci modules that track and combine the data (for up to eight concurrent non-posted pci requests) with their completion data when the completion returns from the pci express link. (refer to chapter 7, ?bridge operations,? for further details.) additionally, the pci interface modules include eight data-holding regi ster sets that are dedicated to tracking the completion progress of eight pci express requests on the pci bus. these registers hold information that uniquely identifies the target location and data quantity requested, for up to eight pci express requests. as the pci module?s state mach ines supply the data requested by the pci express device, these registers track progress toward completion. after a transaction completes, the internal resources dedicated to that tran saction are recovered and readie d to service a new transaction. 4.2 pci express credits pci express credits are issued according to the pci e xpress requirements to manage the internal 8-kb central ram and ensure that no inte rnal memory linked list is overrun.
data path plx technology, inc. 66 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 4.3 latency and bandwidth the pex 8114 can be configured as a pci or pci-x device at up to 133 mhz and 64-bit data bus on the pci-x side, transacting data with the pci express port configured as a 1-, 2-, or 4-lane port. it is anticipated that from a bandwidth-balancing perspective, the pci express port configured as a 4-lane device matches well with the pci-x side operating at 133 mhz and 64 bits. in this matched configuration, expect full bandwidth utilizatio n on the pci express lanes and pci-x bus, with throughput limitations being the external pci expres s and pci-x ports? bandwidth capability and not the pex 8114?s internal bandwidth. a 66-mhz, 64-bi t pci-x port should match a x2 pci express port. it is anticipated that the pex 8114 does not limit the bandwidth of those transactions. bandwidth is affected by many parameters, including but not limited to arbitration latency, cycle startup latency, retries, packet sizes, and external endpoint latency. adjust the parameters within the pex 8114, based on the pci express-to-pci/pci-x bridge r1.0 . 4.3.1 data flow-through latency when the pex 8114 is configured as a pci-x devi ce, operating at 133-mhz clock frequency with a 64-bit wide data bus, and the pci express port is c onfigured as a 4-lane link, expect approximately 300 ns latency through the pex 8114 for header-only packets and approximately 850 ns for headers with 256-byte data packets. this is the latency of data driven from pci-x to pci express. this latency is measured from the frame drop on the pci-x bus, when data is driven into the pex 8114, until the starting symbol of data tlp app ears on the pci express lanes. internal latency of data driven from pci express to pci-x is similar. 4.3.2 pci transaction initial la tency and cycle recovery time in pci mode, when the pex 8114 is a read cycle target, the pex 8114 supplies data or retries the master read request. there are eight cloc k cycles from when the master asserts pci_frame# until the pex 8114 signals a retry or is ready to supply data. this equates to an initial target latency of eight clocks. when the pex 8114 is the write cy cle master, there is one clock cycle from when the master drives pci_frame# until the pex 8114 drives pci_irdy# ready to supply data. this cycle is the address phase, required by the pci r3.0 . there are no initial wait states added by the pex 8114. the pex 8114 is a slow-decode device and supports fast back-to-back addressing. the pex 8114 requires certain cloc k cycles after completion of a previous transaction before it can participate in another transaction. this period is comprised of the clock cycles from the last data phase of the preceding transaction until pci_frame# is asserted on a new transaction, and is referred to as transaction cycle recovery time . the cycle recover time from mastering a pci-x transaction is 10 clock cycles.
january, 2007 pci-x transaction initial latency and cycle recovery time expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 67 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 4.3.3 pci-x transaction initial latency and cycle recovery time in pci-x mode, when the pex 8114 is a read tran saction target, there are seven clock cycles from when the master asserts pci_frame# until the pex 8114 drives a sp lit response to the pci-x read request. when the pex 8114 is a pci-x write cycle ta rget, there are seven clock cycles from when the master asserts pci_frame# until the pex 8114 drives pci_irdy# ready to accept data. this equates to an initial target latency of two clocks. when the pex 8114 is a write or r ead completion master, there are th ree clock cycles from when the pex 8114 asserts pci_frame# until the pex 8114 asserts pci_irdy# indicating that it is ready to drive data. these three clocks cycles are the addre ss, attribute, and turnaround cycles required by the pci-x r2.0a . there are no initial wait states added by the pex 8114. the pex 8114 is a slow-decode device and supports fast back-to-back addressing. the pex 8114 requires certain clock cy cles after the completi on of a previous transaction, before it can participate in another transaction. this period is comprised of the clock cycles from the last data phase of the preceding transaction until pci_ frame# is asserted on a new transaction, and is referred to as transaction cycle recovery time . the cycle recover time for mastering a pci cycle is seven clock cycles. 4.3.4 arbitration latency arbitration latency is the number of pci clock cycles required for the bridge to be granted the bus when it is waiting to make a transfer. this time can vary and is a function of the number of devices on the pci bus and each device?s demand for bus control. at a minimum, the bus can be parked on the bridge and in that case, the arbitration late ncy is 0 clocks. if the bus is not parked on the bridge and not being used by another device, the latency is 1 clock afte r the request. if the bus is being used by another master and hidden arbitration is enabled, the arbitrat ion latency is 1 clock after the other users relinquish the bus. if the bus is being used by another master and hidden arbitration is no t enabled, the arbitration latency is 2 clocks after the other users relinquish the bus.
data path plx technology, inc. 68 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 69 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 5 address spaces 5.1 introduction this chapter discusses the pex 8114 address spaces. 5.2 supported address spaces the pex 8114 supports the following address spaces: pci-compatible configuration (00h to ffh; 256 bytes) pci express extended configuration (100h to fffh) i/o (32-bit; includes isa and vga modes) memory-mapped i/o (32-bit non-prefetchable) prefetchable me mory (64-bit) base address register (bar) access to internal registers the first two spaces, used for accessing conf iguration registers, are described in chapter 6, ?configuration.? the pci express extended configuration space (100h to fffh) is supported only in forward transparent bridge mode, and bars ar e used to access extended configuration space in reverse transparent bridge mode. configuration registers set up for i/o, memory -mapped and prefetchable memory address spaces determine which transactions are forwarded from th e primary bus to the secondary bus and from the secondary bus to the primary bus. the i/o a nd memory ranges are defined by a set of base and limit registers in the configuration header. transacti ons falling within the ranges defined by the base and limit registers are forwarded from th e primary bus to the secondary bu s. transactions falling outside these ranges are forwarded from th e secondary bus to the primary bus. table 5-1 defines which interfaces are primary and s econdary, for the two pex 8114 bridge modes. table 5-1. bridge mode primary and secondary interfaces bridge mode primary interface/bus secondary interface/bus forward transparent bridge pci express pci reverse transparent bridge pci pci express
address spaces plx technology, inc. 70 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.1 i/o space the i/o address space determines whether to forwar d i/o read or i/o write transactions across the bridge. pci express uses the 32-b it short address format (dword-aligned) for i/o transactions. 5.2.1.1 enable bits the following configuration register bits control the bridge response to i/o transactions: command register i/o access enable bit command register bus master enable bit bridge control register isa enable bit bridge control register vga enable bit set the i/o access enable bit to allow i/o transactions to be forwarded downstream. when this bit is not set, all i/o transactions on the s econdary bus are forwarded to the primary bus. if this bit is not set in forward transparent bridge mode, all primary interface i/o requests are completed w ith unsupported request status. if this bit is not set in reverse tr ansparent bridge mode, all i/o transactions are ignored (no pci_devsel# assertion) on the primary (pci) bus. set the bus master enable bit to allow i/o transactions to forward upstream. if this bit is not set in forward transparent bridge mode, all i/o transactions on the seconda ry (pci) bus are ignored. if this bit is not set in reverse transparent bridge mode, all i/o requests on the secondary (pci express) bus are completed with unsupported request status. setting the isa enable bit affects i/o transactions. (refer to section 5.2.1.3, ?isa mode,? for details.) setting the vga enable bit also affects i/o transactions. (refer to section 5.2.1.4, ?vga mode,? for details.) 5.2.1.2 i/o base and limit registers the pex 8114 supports the optional 32-bit i/o addressed access. the following i/o base and limit configuration registers are used to determine wh ether i/o transactions can be forwarded across the bridge: i/o base (upper four bits of the 8-bit regist er correspond to address bits [15:12]) i/o base upper 16 bits (16-bit register correspond s to address bits [31:16]) i/o limit (upper four bits of the 8-bit register correspond to a ddress bits [15:12]) i/o limit upper 16 bits (16-bit register corresponds to address bits [31:16]) the i/o base address consists of one 8-bit register and one 16-bit register. the upper four bits of the 8-bit register define bits [15:12] of the i/o base address. the lower four bits of the 8-bit register determine the i/o address capab ility of this device. the i/o base upper 16 bits register define bits [31:16] of the i/o base address. the i/o limit address consists of one 8-bit register and one 16-bit register. the upper four bits of the 8-bit register define bits [15:12] of the i/o limit. the lower four bits of the 8-bit register determine the i/o address capability of this device, and reflect the value of the same field in the i/o base register. the i/o limit upper 16 bits register defines bits [31:16] of the i/o limit address. because address bits [11:0] are not included in address space decoding, the i/o address range has a granularity of 4 kb, and is always aligned to a 4-kb address boundary sp ace. the maximum i/o range is 4 gb. i/o transactions on the primary bus that fall within the range defined by the base and limit addresses are forwarded downstream to the s econdary bus. i/o transactions on the secondary bus that are within the range are ignored.
january, 2007 i/o space expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 71 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 i/o transactions on the primary bu s that do not fall within the range defined by the base and limit addresses are ignored. i/o transactions on the seco ndary bus that do not fall within the range are forwarded upstream to the primary bus. figure 5-1 illustrates i/o forwarding. when the i/o base address specified by the i/o base and i/o base upper 16 bits registers have a value greater than the i/o li mit address specified by the i/o limit and i/o limit upper 16 bits registers, the i/o range is disabled . in this case, all i/o transactions are forwarded upstream, and no i/o transactions are fo rwarded downstream. figure 5-1. i/o forwarding i/o base i/o limit 4 kb multiple primary bus secondary bus i/o address space downstream upstream
address spaces plx technology, inc. 72 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.1.3 isa mode the bridge control register isa enable bit supports i/o forwarding in systems that include an isa bus. the isa enable bit affects i/o addresses within the range defined by the i/o base and i/o limit registers, located within the fi rst 64 kb of the i/o address space. when the isa enable bit is set, the bridge does not forward i/o transactions downstream on the primary bus, located within the top 768 bytes of each 1-kb block within the first 64 kb of address space. transactions in the lower 256 bytes of each 1-kb block are forwarde d downstream. if the isa enable bit is clear, all addresses within the range defined by the i/o base and i/o limit registers are forwarded downstream. i/o transactio ns with addresses located above 64 kb are forwarded, according to the range defined by the i/o base and i/o limit registers. when the isa enable bit is set, the bridge forwards i/o transactions upstream on the secondary bus, located within the top 768 bytes of each 1-kb block within the first 64 kb of address space, when the address is within the range defined by the i/o base and i/o limit registers. all other transactions on the secondary bus are forwarded upstream if they fall outside the range defined by the i/o base and i/o limit registers. if the isa enable bit is clear, all secondary bu s i/o addresses outside the range defined by the i/o base and i/o limit registers are forwarded upstream. as with all upstream i/o transactions, the command register bus master enable bit must be set to enable upstream forwarding. figure 5-2 illustrates i/o forwarding with the isa enable bit set. figure 5-2. i/o forwarding with isa enable bit set secondary bus isa i/o address space example 000h - 0ffh primary bus 400h - 4ffh 800h - 8ffh 900h - bffh 500h - 7ffh 100h - 3ffh downstream upstream
january, 2007 i/o space expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 73 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.1.4 vga mode the bridge control register vga enable bit enables vga register accesses to forward downstream from the primary to secondary bus, independent of the i/o base and i/o limit registers. the bridge control register vga 16-bit decode bit selects between 10- and 16-bit vga i/o address decoding, and is applicable when the vga enable bit is set. the vga enable and vga 16-bit decode bits control the following vga i/o addresses: 10-bit vga i/o addressing ? address bits [9:0] = 3b0h through 3bbh, and 3c0h through 3dfh 16-bit vga i/o addressing ? address bits [15:0] = 3b0h through 3bbh, and 3c0h through 3dfh these ranges only apply to the fi rst 64 kb of i/o address space. vga palette snooping vga palette snooping is not supported by pci e xpress-to-pci bridges; however, the pex 8114 supports vga palette snooping in reverse transpar ent bridge mode. in forward transparent bridge mode, the bridge control register vga enable bit determines whether vga palette accesses are forwarded from pci express-to-pci. the command register vga palette snoop bit is forced to 0 in forward transparent bridge mode. the bridge control register vga 16-bit decode bit selects between 10- and 16-bit vga i/o palette snooping address decoding, and is applicable when the vga palette snoop bit is set. the vga palette snoop and vga 16-bit decode bits control the following vga i/o palette snoop addresses: 10-bit vga i/o addressing ? address bits [9:0] = 3c6h, 3c8h, and 3c9h 16-bit vga i/o addressing ? address bits [15:0] = 3c6h, 3c8h, and 3c9h the pex 8114 supports the following three modes of vga palette snooping: ignore vga palette accesses when there are no gr aphic agents downstream that must snoop or respond to vga palette access cycles (writes or reads) positively decode and forward vga palette writ es when there are graphic agents downstream from the pex 8114 that must snoop vg a palette writes (reads are ignored) positively decode and forward vga palette writ es and reads when there are graphic agents downstream that must snoop or respond to vga palette access cycles (writes or reads) the bridge control register vga enable bit and command register vga palette snoop bit select the bridge response to vga palette accesses, as defined in table 5-2 . note: x is ?don?t care.? table 5-2. bridge response to vga palette accesses vga enable bit (offset 3ch[19]) vga palette snoop bit (offset 04h[5]) bridge response to vga palette accesses 0 0 ignore all vga palette accesses 0 1 positively decode vga palette writes (ignore reads) 1 x positively decode vga palette writes and reads
address spaces plx technology, inc. 74 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.2 memory-mapped i/o space the memory-mapped i/o address space determines whether to forward n on-prefetchable memory write or read transactions acr oss the bridge. map devices with side effects during reads, such as fifos, into this space. for pci- to-pci express reads, pr efetching occurs in this space when memory read line or memory read line multiple comma nds are issued on the pc i bus. when the memory read line command is used, the data quan tity prefetched is determined by the cache line size value. when a memory read line multiple is used, the data quantity prefetched is determined by the cache line size field (offset 0ch [7:0]) and cache line prefetch line count bit (offset fa0h [4]). for pci-to-pci express transactions, th e prefetched data is flushed af ter the pci device reading the data terminates its first successful r ead transaction during which it receives data. for pci-x-to-pci express reads, the number of bytes to read is determin ed by the transaction size requested in the pci-x attributes. for pci express-to-pci or pci-x reads, the number of bytes to read is determined by the memory read request tlp. transactions that are fo rwarded using this addre ss space are limited to a 32-bit range. 5.2.2.1 enable bits the following configuration register bits control the bridge response to memory-mapped i/o transactions: command register memory access enable bit command register bus master enable bit set the memory access enable bit to allow memory transactions to forward downstream. if this bit is not set, all memory request transactions on the seco ndary bus are forwarded to the primary bus. if this bit is not set in forward transparent bridge mode, all non-posted memory requests are completed with an unsupported request status. posted write data is discarded. if this bit is not set in reverse transparent bridge mode, all memory transact ions are ignored on the primary (pci) bus. set the bus master enable bit to allow memory transactions to forward upstream. if this bit is not set in forward transparent bridge mode, all memory requ est transactions on the secondary (pci) bus are ignored. if this bit is not set in reverse transparent bridge mode, all non-posted memory requests on the secondary (pci express) bus are completed with an unsupported request (u r) status. posted write data is discarded.
january, 2007 memory-mapped i/o space expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 75 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.2.2 memory-mapped i/o b ase and limit registers the following memory base and limit configura tion registers are used to determine whether to forward memory-mapped i/o tran sactions across the bridge: memory base (bits [15:4] of the 16-bit register correspond to address bits [31:20]) memory limit (bits [31:20] of the 16-bit register correspond to a ddress bits [31:20]) memory base register bits [15:4] define memory-mapped i/o base address bits [31:20]. memory limit register bits [31:20] define memory-mapped i/o limit bits [31:20]. bits [3:0] of both registers are hardwired to 0. because address bits [19:0] are not included in the address space decoding , the memory-mapped i/o address range has a granularity of 1 mb, and is always aligned to a 1-mb address boundary space. the maximum memory-mapped i/o range is 4 gb. memory transactions that fall within the range defined by the memory base and memory limit are forwarded downstream from the primary to secondary bus, and memory transactions on the secondary bus that are within the range are ignored. memory tran sactions that do not fall within the range defined by the memory base and limit registers are ignored on the primar y bus, and forwarded upstream from the secondary bus. figure 5-3 illustrates memory-mapped i/o forwarding. when the memory base is programmed with a value greater than the memory limit, the memory-mapped i/o range is disabled. in this case, all memory transaction forwarding is determined by the prefetchable base and limit registers, described in the following section. figure 5-3. memory-mapped i/o forwarding memory base memory limit 1 mb multiple primary bus secondary bus memory-mapped i/o address space downstream upstream
address spaces plx technology, inc. 76 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.3 prefetchable space the prefetchable address space dete rmines whether to forward pref etchable memory write or read transactions across the bridge. map devices, withou t side effects during reads, into this space. for pci-to-pci express reads, prefetching occurs in this space for all memory read commands issued on the pci bus, as defined in table 5-3 . for pci express-to-pci, pci- x, or pci-x-to-pci express reads, the number of bytes to read is determined by the memory read request. therefore, prefetching does not occur. 5.2.3.1 enable bits the prefetchable space responds to the enable bits, as described in section 5.2.2.1, ?enable bits.? table 5-3. pci-to-pci express read prefetching command prefetch memory read (memrd) the pex 8114 prefetches the number of bytes indicated in the prefetch register prefetch space count field (offset fa4h[13:8]). memory read line (memrdline) the pex 8114 prefetches the number of bytes indicated in the cache line size (offset 0ch [7:0]). memory read line multiple (memrdlinemult) the pex 8114 prefetches 1 or 2 cach e lines, as indicated in the cache line prefetch line count bit (offset fa0h[4]). each line contains the number of bytes indicated in the cache line size , up to a maximum of 128 bytes.
january, 2007 prefetchable space expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 77 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.3.2 prefetchable b ase and limit registers the following prefetchable memory base and limit configuration registers are used to determine whether prefetchable memory transactio ns can be forwarded across the bridge: prefetchable memory base (bits [15:4] of the 16-bit register correspond to address bits [31:20]) prefetchable memory base upper (32-bit register corresponds to address bits [63:32]) prefetchable memory limit (bits [31:20] of the 16-bit register correspond to address bits [31:20]) prefetchable memory limit upper (32-bit register corresponds to address bits [63:32]) prefetchable memory base register bits [15:4] define prefetch able memory base address bits [31:20]. prefetchable memory limit register bits [31:20] define prefetchable memory limit bits [31:20]. bits [3:0] of both registers are hardwired to 1h, indicating 64-bit addressing. the default 64-bit addressing bit can be cleared to 0h during serial eeprom load for systems that must run in 32-bit addressing mode. for 64-bit addressing, the prefetchable memo ry base upper and prefetchable memory limit upper registers are also used to define the space. because address bits [19:0] are not included in the address space d ecoding, the prefetchable memory address range has a granularity of 1 mb, and is always aligned to a 1-mb address boundary space. the maximum prefetchable memory range is 4 gb with 32-bit addressing, and 2 64 with 64-bit addressing. memory transactions that fall within the range defined by the prefetchable memory base and limit registers are forwarded downstream from the primary to secondary bus, and memory transactions on the secondary bus that are within the range are ignored. memory transactions that do not fall within the range defined by the prefetchable memory base and limit registers are ignored on the primary bus and forwarded upstream from the secondary bus (provided they are not in the address range defined by the memory-mapped i/o address register set). figure 5-4 illustrates memory-mapped i/o and prefetchable memory forwarding. when the prefetchable memory base is programmed with a value greater than the prefetchable memory limit , the prefetchable memory range is disabl ed. in this case, all memory transaction forwarding is determined by the memory-mapped i/o base and limit registers. all four prefetchable base and limit registers must be considered when disabling the prefetchable memory range. in figure 5-4, reworded ?prefetchable and me mory-mapped i/o memory space? to ?prefetchable memory and memory-mapped i/o space.?
address spaces plx technology, inc. 78 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 figure 5-4. memory-mapped i/o and prefetchable memory forwarding prefetchable memory base prefetchable memory limit primary bus secondary bus prefetchable memory and memory-mapped i/o space memory-mapped i/o limit memory-mapped i/o base 4-gb address boundary space dac dac dac dac sac sac sac sac sac sac sac sac sac = single address cycle dac = dual address cycle 1 mb multiple 1 mb multiple downstream upstream
january, 2007 prefetchable space expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 79 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 5.2.3.3 64-bit addressing unlike memory-mapped i/o memory that must reside below the 4-gb address boundary space, prefetchable memory can reside below, above, or span the 4-gb address boundary space. memory locations above the 4-gb address boundary space must be accessed using 64-bit addressing. pci express memory transactions that use the s hort address (32-bit) format can target the non-prefetchable memory space, or a prefetchable memory wi ndow located below the 4-gb address boundary space. pci express memory transactions that use the long address (64 bit) format can target locations anywhere in 64-bit memory space. pci memory transactions that us e single address cycles can only target locations below the 4-gb address boundary space. pci memory transactions that use dual a ddress cycles can target locations anywhere in 64-bit memory space. the first address phase of a dual address transaction contains the lower 32 bits of the address, and the second addres s phase contains the upper 32 bits of the address. if the upper 32 bits of the address are 0, a single address transaction is performed. forward transparent bridge mode when the prefetchable memory base upper and prefetchable mem ory limit upper registers are both cleared to 0, addresses located ab ove the 4-gb address boundary space are not supported . in forward transparent bridge mode, if a pci express me mory transaction is detected with an address located above 4 gb, the transaction is completed wi th unsupported request status. all dual address transactions on the pci bus are forwar ded upstream to the pci express interface. when the prefetchable memory is located enti rely above the 4-gb address boundary space, the prefetchable memory base upper and prefetchable memory limit upper registers are both set to non-zero values. if a pci express memory transacti on is detected with an address located below the 4-gb address boundary space, the tr ansaction is completed with unsu pported request status, and all single address transactions on the pci bus are forwarded upstre am to the pci express interface (unless they fall within the memory-mapped i/o range). a pci express memory transaction located above 4 gb, that falls within the range defined by the prefetchable base , prefetchable memory base upper , prefetchable memory limit , and prefetchable memory limit upper registers, is forwarded downstream and becomes a dual address cycle on the pci bus. if a dual address cycle is detected on the pci bus located outside the range defined by th ese registers, it is forwarded upstream to the pci express interface. if a pci express memory tran saction located above the 4-gb address boundary space does not fall within the range defined by these re gisters, it is completed with unsupported request status. if a pci dual address cycle falls within the range determined by these registers, it is ignored. when the prefetchable memory spans the 4-gb address boundary space, the prefetchable memory base upper register is clear ed to 0, and the prefetchable memory limit upper register is set to a non-zero value. if a pci express me mory transaction is detected wi th an address located below 4 gb, and is greater than or equal to the prefetchable memory base addr ess, the transaction is forwarded downstream. a single address trans action on the pci bus is forwar ded upstream to the pci express interface if the address is less th an the prefetchable memory base address. if a pci express memory transaction located above 4 gb is less than or equal to the prefetchable memory limit register, it is forwarded downstream to the pci bu s as a dual address cycle. if a dual address cycle on the pci bus is less than or equal to the prefetchable memory limit register, it is ignored. if a pci express memory transaction located above 4 gb is greater than the prefetchable memory limit register, it is completed with unsupported request status. if a dual addr ess cycle on the pci bus is greater than the prefetchable memory limit register, it is forwarded upstream to the pci express interface.
address spaces plx technology, inc. 80 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 reverse transparent bridge mode when the prefetchable memory base upper and prefetchable mem ory limit upper registers are both cleared to 0, addresses located ab ove the 4-gb address boundary space are not supported . in reverse transparent bridge mode, if a dual addr ess transaction on the pci bus is detected, the transaction is ignored. if a pci exp ress memory transaction is detected with an address located above the 4-gb address boundary space, it is forwarded upstream to the pci bus as a dual address cycle. when the prefetchable memory is located enti rely above the 4-gb address boundary space, the prefetchable memory base upper and prefetchable memory limit upper registers are both set to non-zero values. the pex 8114 ignores all single address memory transactions on the pci bus, and forwards all pci express memory transactions with addresses lo cated below the 4-gb address boundary space upstream to the pci bus (unless they fall within the memory-mapped i/o range). a dual address transaction on the pci bus th at falls within the range defined by the prefetchable base , prefetchable memory base upper , prefetchable memory limit , and prefetchable memory limit upper registers is forwarded down stream to the pci express interface. if a pci express memory transaction is located above the 4-gb address boundary space and fa lls outside the range defined by these registers, it is forwarded upstream to the pc i bus as a dual address cy cle. if a dual address transaction on the pci bus does not fall within the ra nge defined by these registers, it is ignored. if a pci express memory transaction located above 4 gb fall s within the range defined by these registers, it is completed with unsupported request status. when the prefetchable memory spans the 4-gb address boundary space, the prefetchable memory base upper register is cleared to 0, and the prefetchable mem ory limit upper register is set to a non-zero value. if a pci single addr ess cycle is greater th an or equal to the prefetchable memory base address, the transaction is forwarded downstr eam to the pci express interface. if a pci express memory transaction is det ected with an address located below th e 4-gb address boundary space, and is less than the prefetchable memory base address, the tran saction is forwarded upstream to the pci bus. if a dual address pci transacti on is less than or equal to the prefetchable memory limit register, it is forwarded downstream to the pci express interf ace. if a pci express memory transaction located above the 4-gb address boundary sp ace is less than or equal to the prefetchable memory limit register, it is completed with unsupported request st atus. if a dual address pci transaction is greater than the prefetchable memory limit register, it is ignored. if a pci express memory transaction located above the 4-gb address bo undary space is greater than the prefetchable memory limit register, it is forwarded upstream to the pci bus as a dual address cycle. 5.2.4 base address register addressing the base address registers (bars) provide me mory-mapped access to internal configuration registers. this method of accessing inte rnal registers is used exclusively to access the pci express extended register set when operating as a revers e pci bridge, which has no other method of accessing without access to the higher configuration addresses. all accesses using the bars return 1 dword of data. the bars do not affect data forwarding thro ugh the bridge that uses memory i/o, memory- mapped, or prefetchable memory. the pex 8114 defaults to a non-prefetchable 32- bit bar access, using bar0 and leaving bar1 unused. the pex 8114 can be configured by serial eeprom to support 64-bit non-prefetchable bar access, using both bar0 and bar1 to create a 64-bit bar, by setting the base address 0 register memory map type field (offset 10h[2:1] to 10b. addresses transmitted to the bar window are linear ly translated into regi ster address accesses. the n th location of the bar maps to the n th configuration register. access to bar locations that do not contain registers corresponding to that address retu rn ur in forward transparent bridge mode and 0 in reverse transparent bridge mode. for further details, refer to chapter 6, ?configuration.?
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 81 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 6 configuration 6.1 introduction configuration requests are initiated by the root complex in a pci express system and by the pci or pci-x host or central resource function in a pci system. all devices located within a pci express or pci system include a configuration space accessed us ing configuration transactions to configure operational characteristics of the device. when the pex 8114 operates as a forward bridge, all configurations originate at the pci express root complex. the pex 8114 is configured by the root complex. the pex 8114 register set appears as a type 1 pci express bridge register set with a device id of 8114h and additional device-specific registers. the pci express bridge register set is enumerated and configured by the bios according to pci express conventions. configuration or change s to the additional device-specific registers is optional, as changes to the device-specific register s are not required to allow the pex 8114 to function. pci devices located downstream from the pex 8114 are configured by the root complex through the pex 8114. when the pex 8114 operates as a re verse bridge, all configurations or iginate at the pci-x or pci host. the pci-x host configures the pex 8114, using pci transactions. the pci-x host also configures pci express devices, located downstream from the pe x 8114, by transmitting pci transactions to the pex 8114, which the bridge converts into pci expre ss configuration transactions and then forwards to the pci express devices downstream. in reverse transparent bridge mode, the pex 8114 re gister set appears as a type 1 pci bridge register set with a device id of 8114h and additional device- specific registers. the pc i bridge register set is enumerated and configured by the bios accordin g to pci bridge conven tions. configuration or changes to the additional device- specific registers is optional, as changes to the device-specific registers are not required to allow the pex 8114 to function. type 0 configuration transactions are used to access the internal pex 8114 configuration registers. when the pex 8114 is configured as a forward or reverse bridge, type 1 configuration transactions are transmitted into the pex 8114 to access devices downstream from the pex 8114. these type 1 configurations are converted to type 0 transactions, if they are targeted to the device on the bus directly below the pex 8114. if the transactio n is a target for a bus downstr eam from the bus located directly below the pex 8114, the transaction is passed through the pex 8114 as a type 1 configuration. if the transaction is not targeted for the pex 8114, or devices located downstream from the pex 8114, the transaction is rejected.
configuration plx technology, inc. 82 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 the configuration address is formatted as follows: pci express 31 24 23 19 18 16 15 12 11 8 72 10 bus number device number function number reserved extended register address register address reserved pci type 0 (at initiator) 31 16 15 11 10 8 72 10 single bit decoding of device number reserved function number register number 00 pci type 0 (at target) 31 11 10 8 72 10 reserved function number register number 00 pci type 1 31 24 23 16 15 11 10 8 72 10 reserved bus number device number function number register number 01
january, 2007 type 0 configuration transactions expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 83 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.2 type 0 configuration transactions the pex 8114 responds to type 0 configuration tran sactions on its primary bus that address the pex 8114 configuration space. a type 0 configuratio n transaction is used to configure the pex 8114, and is not forwarded downstream to the secondary bus. the pex 8114 ignores type 0 configuration transactions on its secondary bus. type 0 configuration transactions result in the transfer of 1 dword. if configuration write data is poisoned, the data is discarded and a non-fatal error message is generated, if enabled. 6.3 type 1 configuration transactions type 1 configuration transactions are used for de vice configuration in a hi erarchical bus system. transparent bridges and switches are the only devices that respond to type 1 configuration transactions. type 1 conversion to special cycles are not supported . when the pex 8114 operates as a type 1 transparent bridge, configuration tr ansactions are used when the transaction is intended for a device residing on a bus other than the one that issued the type 1 request. the bus number field in a configuration transaction request specifies a unique bus in the hierarchy, on which the transaction target resides. the bridge compares the specifi ed bus number with two pex 8114 configuration registers ? secondary bus number and subordinate bus number ? to determine whether to forward a type 1 configuration transaction across the bridge. when the primary interface receives a type 1 configuration transaction, the following tests are applied, in sequence, to the bus number field to determine how to handle the transaction: 1. when the bus number field is equal to the secondary bus number register value, the pex 8114 forwards the configuration request to the seco ndary bus as a type 0 configuration transaction. 2. when the bus number field is not equal to the secondary bus number register value, but is within the range of the secondary bus number and subordinate bus number (inclusive) registers, the type 1 configuration request is specify ing a bus located behind th e bridge. in this case, the pex 8114 forwards the configuration request to the secondary bus as a type 1 configuration transaction. 3. when the bus number field does not satisfy the above criteria, the type 1 configuration request is specifying a bus that is not located behind the bridge. in this case, the configuration request is invalid. if the primary interface is pci expr ess, a completion with unsupported request (ur) status is returned. if the primar y interface is pci, the configuratio n request is ignored, resulting in resulting in delivery of ffff_ffffh or a target abort. if the bridge control register master abort mode bit (offset 3ch [21]) is set, the pex 8114 replies to the pci requester?s follow-on non-posted requests with a target abort. if the master abort mode bit is not set, the pex 8114 replies to the pci requester?s follow-on non-posted requests with ffff_ffffh.
configuration plx technology, inc. 84 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.4 type 1-to-type 0 conversion the pex 8114 performs a type 1-to-type 0 conversion when the type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. the pex 8114 must convert the type 1 configuration transaction to type 0, to allow the downstream device to respond to it. type 1-to-type 0 conversions are performed only in the downstream direction. the pex 8114 generates type 0 configuration transactions only on the secondary interface. 6.4.1 forward transparent bridge mode the pex 8114 forwards a type 1 transaction on the pci express interface to a type 0 transaction on the pci bus, if the type 1 configuration request bus number field is equal to the secondary bus number register value. the pex 8114 then performs the follow ing steps on the secondary interface: 1. clears address bits ad[1:0] to 00b. 2. derives address bits ad[7:2] directly from the configuration request register address field. 3. derives address bits ad[10:8] directly from the configuration request function number field. 4. clears address bits ad[15:11] to 00h. 5. decodes the device number field and sets a single address bit within the range ad[31:16] during the address phase. 6. verifies that the extended register address field in the configuration request is 0h. if the value is non-zero, the pex 8114 does not forward the trans action, and treats it as an unsupported request on the pci express interface, and a r eceived master abort on the pci bus. type 1-to-type 0 transactions are perf ormed as non-posted transactions.
january, 2007 reverse transparent bridge mode expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 85 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.4.2 reverse transparent bridge mode the pex 8114 forwards a type 1 transaction on the pci bus to a type 0 transaction on the pci express interface, if the following are tr ue during the pci address phase: address bits ad[1:0] are 01b. the type 1 configuration request bus number field (ad[23:16]) is equal to the secondary bus number register value. the bus command on pci_c/be[3:0]# (32-bit bus) or pci_c/be[7:0]# (64-bit bus) is a configuration write or read. the type 1 configuration request device number field (ad[15:11]) is 0h. if it is non-zero, the pex 8114 ignores the transaction, resulting in a master abort. the pex 8114 then creates a pci express confi guration request, accord ing to the following: 1. sets the request type field to configuration type 0. 2. derives the register address field [7:2] directly from the configuration request register address field. 3. clears the extended register address field [11:8] to 0h. 4. derives the function number field [18:16] directly from the configuration request function number field. 5. derives the device number field [23:19] directly from the configuration request device number field (forced to 0h). 6. derives the bus number field [31:24] directly from the configuration request bus number field. type 1-to-type 0 transactions are perf ormed as non-posted transactions.
configuration plx technology, inc. 86 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.5 type 1-to-type 1 forwarding type 1-to-type 1 transaction forwarding provides a hi erarchical configuratio n mechanism when two or more levels of bridges are used. when the pex 8114 detects a type 1 configuration transaction intended for a pci bus downstream fr om the secondary bus, it forwards the transaction, unchanged, to the secondary bus. in this case, the transaction target does not reside on the pex 8114? s secondary interface, but is located on a bus segment farther downstream. ultimately, this transaction is converted to a type 0 transaction by a downstream bridge. 6.5.1 forward transparent bridge mode the pex 8114 forwards a type 1 transaction on the pci express interface to a type 1 transaction on the pci bus, if the following are true: a type 1 configuration transaction is detected on the pci express interface the value specified by the bus number field is within the range of bus numbers between the secondary bus number (exclusive) and subordinate bus number (inclusive) the pex 8114 then performs the follow ing steps on the secondary interface: 1. generates address bits ad[1:0] as 01b. 2. generates pci register number, function number, device number, and bus number directly from the pci express configuration request register address , function number , device number , and bus number fields, respectively. 3. generates address bits ad[31:24] as 00h. 4. verifies that the extended register address field in the configuration request is 0h. if the value is non-zero, the pex 8114 does not forward the transaction, and returns a completion with unsupported request status on the pci express interface, and a received master abort on the pci bus. type 1-to-type 1 forwarding transactions are performed as non-posted transactions.
january, 2007 reverse transparent bridge mode expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 87 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.5.2 reverse transparent bridge mode the pex 8114 forwards a type 1 transaction on the pci bus to a type 1 transaction on the pci express interface, if the following are tr ue during the pci address phase: address bits ad[1:0] are 01b. the value specified by the bus number field is within the range of bus numbers between the secondary bus number (exclusive) and subordinate bus number (inclusive). the bus command on pci_c/be[3:0]# (32-bit bus) or pci_c/be[7:0]# (64-bit bus) is a configuration write or read. the pex 8114 then creates a pci express confi guration request, accord ing to the following: 1. sets the request type field to configuration type 1. 2. derives the register address field [7:2] directly from the configuration request register address field. 3. clears the extended register address field [11:8] to 0h. 4. derives the function number field [18:16] directly from the configuration request function number field. 5. derives the device number field [23:19] directly from the configuration request device number field. 6. derives the bus number field [31:24] directly from the configuration request bus number field. type 1-to-type 1 forwarding transactions are performed as non-posted transactions. 6.6 pci express enhanced configuration mechanism the pci express enhanced config uration mechanism adds four additional bits to the register address field, thereby expanding the space to 4,096 bytes. the pex 8114 forwards co nfiguration transactions only when the extended register address bits are all 0. this prevents address aliasing on the pci bus that does not support extended register addressing. when a configuration transactio n targets the pci bus and contains a non-zero value in the extended register address field, the pex 8114 treats the transaction as if it received a master abort on the pci bus. the pex 8114 then performs the following steps: 1. sets the appropriate status bits for the destinatio n bus, as if the transaction executed and resulted in a master abort. 2. generates a pci express completion with unsupported request status.
configuration plx technology, inc. 88 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.7 configuration retry mechanism 6.7.1 forward transparent bridge mode bridges must return a completion for all configuration requests that traverse the bridge from pci express-to-pci prior to expiration of the completion timeout timer in the root complex. this requires that bridges take ownership of all config uration requests forwarded across the bridge. if the configuration request to pci successfully completes prior to the bridge timer expiration, the bridge returns a completion with successf ul status to pci express. if th e configuration request to pci encounters an error condition prior to the bridge timer expiration, the bridge returns an appropriate error completion to pci express. if the configuration request to pci does not successfully complete or with an error prior to timer expiration, the bridge returns a completion with configuration retry status (crs) to the pci express interface. after the pex 8114 returns a completion with crs to pci express, the pex 8114 continues to allow the configuration transaction to re main alive on the pci bus. the pci r3.0 states that once a pci master detects a target retry, it must continue to retry the tran saction until at least 1 dword is transferred. the pex 8114 retries the transaction until the transaction completes on the pci bus or until the pci express to pci retry timer expires. when the configuration transaction completes on the pci bus after the return of a completion with crs on the pci express interface, the pex 8114 dis cards the completion info rmation. bridges that implement this option are also required to implement the device control register bridge configuration retry enable bit [15]. if this bit is cleared, the bridge does not return a completion with crs on behalf of configuration requests forwarded across the bri dge. the lack of a completion results in eventual completion timeout at the root complex. bridges, by default, do not return crs for configuration requests to a pci device located behind the bridge. this can result in lengthy completion delays that must be comprehended by the completion timeout value in the root complex. 6.7.2 reverse transparent bridge mode in reverse transparent bridge mo de, when the pex 8114 detects a crs, it resends the configuration request to the pci express device to allow the conf iguration request to remain alive, and reset its internal timer. if the pex 8114 is in pci mode an d the internal timer times out before receiving a crs or error message from the pci express device, the pex 8114 replies with ffff_ffffh if the bridge control register master abort mode bit (offset 3ch [21]) is not set. otherwise, it causes a target abort if the master abort mode bit is set. if the pex 8114 is in pci-x mode, it transmits a split completion with a target abort error message.
january, 2007 configuration methods expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 89 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.8 configuration methods the pex 8114 supports the standard configuration methods and maintains several device-specific configuration methods. the pex 8114 supports forwar d and reverse transparent bridge modes. each mode is slightly different fr om a configuration perspective. the basic configuration methods include: pci express extended configuration cycles pci configuration cycles bar0/1 memory-mapped configuration of device-specific registers address and data pointer method for register access the pci express extended configuration method provides a pci express r1.0a -compliant method for configuring pci express registers. the pci configuration method provides a pci r3.0 -compliant method for accessing pci registers. the bar0 and bar1 configuration method provides 32- or 64-bit memory-mapped access to registers. this is typically used to access registers that cannot be accessed by pci express extended or conventional pci configurations. in general, bar0 and bar1 point to 8 kb of memory cycle-accessible address space. th is 8 kb of space is used to write and read registers within, or downstream from, the pe x 8114. the 8 kb of memory-mapped space accesses registers in a slightly different manner in forwar d and reverse transparent mo des. the differences are explained in the next section. the address and data pointer method provides two registers within the configuration space for reverse transparent mode. one register represents an address in the pci/ pci express hierarchy, the other is a data value regi ster. by loading the address register with a target address, then writing or reading the data register, a location in the address space can be written or read. 6.8.1 configuration method s intent and variations configuration register accesses must be supported in all primary oper ation modes. these modes include forward and reverse transparent. each supported configuration method provides access to at least some of the configuration regist ers. certain configuration method s provide access to conventional pci registers, while others provide easy access to devi ce-specific registers. by providing a combination of configuration methods, the pex 8114 allows conventional pci access to many registers and logical simple access to device-specific registers, as well as downstream device registers. operation modes slightly vary; therefore, certain configuration met hods also vary. the following sections explain the basic capability differences.
configuration plx technology, inc. 90 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.8.2 pci express extend ed configuration method the pci express extended configuration method prov ides forward transparent bridges with access to the standard set of pci express registers. this configuration method provides pci-sig-compliant access to the pex 8114 pci-sig-defined registers. it also provides access to pci-sig-compliant access to registers in downstream devices when the pex 8114 is used in forward transparent bridge mode. this method is, however, confined to accessing th e pci express-defined registers and is not used to access the pex 8114 device-specific registers. in forward transparent bridge mode, memory-m apped access is supported to access device-specific pex 8114 registers. address and data pointer register access is not supported in forward transparent bridge mode. therefore, the pex 8114 devi ce-specific registers can only be accessed by memory-mapped access. 6.8.3 pci configuration cycles pci configuration cycles are used in reverse transp arent bridge mode to a ccess the standard 256-byte pci-defined register space. this method provides conventional pci register access that functions with conventional pci bios; however, it does not provide access in the following: reverse transparent bridge mode to downst ream devices? pci express extended registers reverse transparent bridge mode to down stream devices? devi ce-specific registers in reverse transparent bridge mode, use the memo ry-mapped or address and data pointer method to access the downstream devices? pci express extende d registers or the de vice-specific registers. 6.8.4 bar0/1 device-specifi c register memory-mapped configuration bar0 and bar1 are used to provide 32- or 64-bit memory-mapped access to the device-specific registers. the use of memory-mapped access is sligh tly different in forward transparent bridge mode than it is in reverse transparent bridge mode. forward transparent bridge mode ? memory-mapped access provides access to pex 8114 internal device-specific registers. reverse transparent bridge mode ? memory-mapped access provides access to all pex 8114 internal registers, as well as to downstream pci express device registers. this memory-mapped method allows pci hosts (which support only conventional pci configuration registers) to access devices on the downstream pci express side of the bridge, using pci express extended configuration space. bar0 and bar1 device-specific register me mory-mapped configuration can be disabled by setting the disable bar0 bit (offset fa0h [7]). by default, this bit is cleared; however, it can be set by way of serial eeprom load. when this bit is set, bar0 is lo aded with all zeros (0) at reset, and appears to the operating system as disabled.
january, 2007 address and data pointer configuration method expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 91 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6.8.5 address and data po inter configuration method in reverse transparent bridge mode, the address an d data pointer configuration method provides the pci host with access to all pex 8114 extended register s, as well as all registers of pci express devices on links located downstream from the pex 8114. access to the configuration registers through the memory-mapped or address and data pointer configuration method is intended; however, both me thods cannot be used concurrently. access to the configuration registers by way of the address an d data pointers, which were accessed by the bar0/1 memory-map access (double-indirect access) results in undefined data. 6.8.6 configuration specifics this section details how configuration cycles f unction in forward and reverse transparent bridge modes and defines the register address ranges accessed by each cycle type. the three operational modes are described separately, and in each description a table is provided that defines the recommended method for accessing the register ra nges, located within and downstr eam from the pex 8114. following the table of recommended access methods, the methods are described as they function in that mode. 6.8.6.1 forward transpa rent bridge mode in forward transparent bridge mode, access to all re gisters located within a nd downstream from the pex 8114 is provided according to table 6-1 . table 6-1. access to registers during forward transparent bridge mode target register type register location intended configuration method pex 8114 pci express-defined registers pex 8114 registers 00h through 1c7h, fb4h through fffh pci express extended configuration pex 8114 device-specific registers p ex 8114 registers fffh to fb3h bar0/1 memory-mapped configuration downstream device pci registers downstream bus with register addresses 00h through ffh pci express extended configuration accessing of pci-defined registers ? first 256 bytes downstream device device-specific registers downstream device-specific not supported
configuration plx technology, inc. 92 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pci express extended configuration access in forward transparent bridge mode in forward transparent bridge mode (as in all other modes), the pci express extended configuration method functions, as described in the pci express r1.0a , and as previously described. the pex 8114 makes no non-standard modifications to the standard pci express extended configuration method. forward transparent memory-mapped bar0/1 access to internal registers in forward transparent bridge mode, bar0 and bar1 are used to provide 32- or 64-bit memory- mapped access to internal configuration registers. when bar0 and bar1 are enumerated according to pci convention and the bridge op eration description herein, access to a 4-kb memory-mapped window into the configuration registers is provided. th e 4-kb window provides access to all pci express extended register addresses. the memory-ma pped window locations are linearly mapped to configuration register space, acco rding to the following equation: for n = 0 through 4 kb-1; memory-mapped address base+ n access register n all internal registers can be accessed through memory-mapped access in forward transparent bridge mode. 6.8.6.2 reverse transparent bridge mode in reverse transparent bridge mode, access to all re gisters located within an d downstream from the pex 8114 is provided according to table 6-2 . table 6-2. access to registers during reverse transparent bridge mode target register type register location intended configuration method pex 8114 pci-defined registers pex 8114 register s 00h through ffh conventional pci configuration pex 8114 pci and device-specific registers pex 8114 registers 100h through fffh bar0/1 memory-mapped configuration address and data pointer configuration downstream device pci type 0 bridge register set from register 00h through ffh for enumeration downstream bus with register addresses 00h through ffh conventional pci configuration downstream device pci express extended registers pci express extended registers (includes registers 100h through fffh) bar0/1 memory-mapped configuration address and data pointer configuration downstream device device-specific registers downstream device-specific bar0/1 memory-mapped configuration address and data pointer configuration
january, 2007 configuration specifics expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 93 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 conventional pci configuration access in reverse transparent bridge mode, the conventional pci configuration method functions, as described in the pci r3.0 , and as previously described. the pex 8114 makes no non-standard modifications to the pci configur ation method. using th e pci configuration method, accesses can be made to the pex 8114 standard 256 bytes of pci register space and the first 256 bytes of any downstream pci express device located on links do wnstream from the pex 8114. because of the limitation of having access to only the first 256-byte offsets of the 4-kb extend ed register space of the downstream pci express device, an extended memory -mapped method is used to access the additional pci express registers of the downstream devices . the extended memory-mapped access method is described in the next section. reverse transparent memory-mapped bar0/1 access to internal extended registers and downstream device registers in reverse transparent bridge mode, bar0 and bar1 are used to provide 32- or 64-bit memory- mapped access to the pex 8114 internal configur ation registers and 4-kb pci express extended configuration register space of pci express devices on link(s) located down stream from the pex 8114. when bar0 and bar1 are enumerated, according to pci co nvention and according to the bridge operation description herein, access is allowed to an 8-kb memory-mapped window into the configuration registers of a device in the hierarchy that originates at the pex 8114. the 8-kb window provides access to all pex 8114 pci express exte nded register addresses and the pci express extended address space of all downstream pci e xpress devices. the lower 4 kb of memory-mapped space, locations 0 through 4 kb-1 (fffh), is a 4-kb access window into configuration space that allows writing and reading of registers. the memory-mapped location at 4 kb (1000h) is a pointer to a register set on the bus hierarchy, which indicates th e start location in the access window. the pointer?s contents create an address, defined in table 6-3 . when a pex 8114 internal register is accessed, the memory-mapped access cycle causes an internal register read. when the register accessed is in a device located downstream from the pex 8114, the memory-mapped access cycle is converted to a conf iguration access, which is transmitted down the link. the memory-mapped window is linearly mapped to the config uration register space of the register set pointed to by the point er, according to the following equation: for n = 0: 4 kb-1; memory-mapped address base+ n access register n set the configuration enable bit to 1, to enable downstr eam memory-mapped accesses. all pex 8114 internal registers and downstream pci expr ess devices can be accessed through the memory- mapped method. table 6-3. reverse transparent configuration address pointer at memory-mapped location 1000h 31 30 28 27 20 19 15 14 12 11 0 || | | | | || | | | --------------------- forced to 0 || | | ----------------------------------------------- function number [2:0] || | ------------------------------------------------------------- device number [4:0] || ------------------------------------------------------------------------------------ bus number [7:0] | -------------------------------------------------------------------------------------------------------- not used --------------------------------------------------------------------------------------------------------------- configuration enable bit
configuration plx technology, inc. 94 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 reverse transparent address and data pointer register access to internal and extended registers and downstream device registers in reverse transparent bridge mode, two register s in pex 8114 configurat ion space provide indirect access into any configuration register in the pe x 8114 or any pci express device located downstream from the pex 8114. the address pointer register is a 32-bit register, located at offset f8h . this register points to the address of a unique register located within or downstream from the pex 8114. the address pointer bits are defined in table 6-4 . the data register is a 32-bit register lo cated at offset fch. when this register is written or read, the 32-bit register value pointed to by th e address pointer is written or read. set the configuration enable bit to 1 to enable address and da ta pointer accesses. when a pex 8114 internal register is accessed using the address a nd data pointer access cycle, the pex 8114 executes an internal register access. when the register accesse d is in a device located downstream from the pex 8114, the address and data pointer access cycl e is converted to a configuration access, which is transmitted down the link. all internal pex 8114 registers and downstream pci express devices can be accessed through the address and data pointer method in reverse transparent bridge mode. table 6-4. reverse transparent configuration address pointer at offset f8h 31 30 26 25 16 15 8 73 20 || | | | | | | | | | ----- function number [2:0] | | | | --------------------- device number [4:0] || | ------------------------------------------ bus number [7:0] | | | | -------------------------------------------------------------------------- register dword address [9:0] (32-bit access; lsbs = 00b) | ---------------------------------------------------------------------------------------------------- reserved --------------------------------------------------------------------------------------------------------------- configuration enable
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 95 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 7 bridge operations 7.1 introduction the pex 8114 supports pci express transaction bri dging to a pci bus operating in pci or pci-x mode. to simplify the descriptions, the pex 8114 operational description is divided into the following types: pci-to-pci express transactions pci-x-to-pci express transactions pci express-to-pci transactions pci express-to-pci -x transactions the following sections discuss thes e transactions. transaction transf er failures and general compliance are also discussed. 7.2 general compliance the pex 8114 complies with the following speci fications for the listed processes and modes: pci r3.0 ? pci mode pci-x r1.0b or pci-x r2.0a ? pci-x mode pci express r1.0a ? pci express port pci express-to-pci/pci-x bridge r1.0 ? pci and pci express transaction ordering rules
bridge operations plx technology, inc. 96 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.3 pci-to-pci expr ess transactions when a pci device attempts a write from the pc i bus to the pci express interface, the pex 8114 translates pci burst write transactions into pci express data tlps. in the most basic transaction, the pex 8114 receives a data burst on the pci bus an d transfers the data into a pci express tlp. 7.3.1 pci-to-pci express flow control the pex 8114 ensures that the internal resources for st oring data are not overrun. if an internal data storage resource is full, or approaching full in certain cases, the pex 8114 issues retries to all new request transactions and only accepts completions or requests of types without depleted resources. 7.3.2 pci-to-pci express ? pci posted write requests when servicing posted writes, no completion information is returned to the pci device that originated the transaction, and when the tlp is transmitted to the pci express link, the transaction is considered complete. table 7-1 defines pci posted write requests and the resultant pci express transactions created in response to the posted write. table 7-1. pci posted write requests initial posted pci transactions resultant pci express transaction interrupt ack not supported special cycle not supported dual address cycle mwr tlp, up to ma ximum packet size; type=00000b, fmt=11b memory write mwr tlp, up to maximu m packet size; type=00000b, fmt=1xb memory write and invalidate mwr tlp, up to maximum packet size; type=00000b, fmt=1xb
january, 2007 pci-to-pci express ? pci non-posted requests expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 97 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.3.3 pci-to-pci express ? pci non-posted requests on non-posted pci transactions, the pex 8114 issues a retry to the pci originator when it receives the first request. the retry indicates that the non-posted transaction was not completed on the pci express port. in addition to transmitting the retry in response to the first non-posted pci request, the pex 8114 also creates and issues a non-po sted tlp on the pci express link. table 7-2 defines all non-posted requests and their resultant pci express requests. di rect non-posted transac tions to prefetchable or non-prefetchable memory space. note: ?x? indicates ?don?t care.? 7.3.4 pci-to-pci express ? pci non-posted transactions until pci express completion returns after the initial non-posted request that caused the resultant transaction is issued on the pci express interface, subsequent requests from the pci devi ce are retried until the pex 8114 detects that the pci express link transmitted a completion tlp matching the request. the pex 8114 supports up to eight parallel non-posted requests. if the internal state machines indi cate that the link is down, and the bridge control register master abort mode bit (offset 3ch [21]) is set, the pex 8114 replies to the pci requester?s follow-on non-posted re quests with a target abort. if the master abort mode bit is not set, the pex 8114 replies to the pci requester?s follow-on non-posted requests with ffff_ffffh. table 7-2. pci non-posted requests initial non-posted pci transactions resultant pci express transaction i/o write iowr tlp; lengt h=1; type=0010b, fmt=10b i/o read iord tlp; lengt h=1; type=0010b, fmt=00b memory read memrd tlp, up to pr efetch size; type=0000b, fmt=0xb configuration write cfgwr0/1 tlp; length=1; type=00100b, fmt=10b configuration read cfgrd0/1 tl p; length=1; t ype=00100b, fmt=00b configuration type 1 write cfgwr1 tlp; length=1; type=00100b, fmt=10b configuration type 1 read cfgrd1 tl p; length=1; type=00100b, fmt=00b dual address cycle fmt=01b for memory reads and memory writes memory read line memrd tlp, up to ca che line size; t ype=00000b, fmt=1xb memory read line multiple one or more memrd tlp, up to cach e line size; type=0000b, fmt=1xb
bridge operations plx technology, inc. 98 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.3.5 pci-to-pci express ? pc i requests do not contain predetermined lengths pci read requests do not contain an indication of th e quantity of data they require; however, the tlps that the pex 8114 issues to the pci express device must indicate data request quantities. the pex 8114 treats memory reads to prefetchable space differently than it treats memory reads to non-prefetchable space, and di fferently than it treats memory read lines and memory read line multiples. the pex 8114 resolves the data request quantity ambiguity, as discussed in the following sections. 7.3.5.1 memory read requests to non-prefetchable space when the pex 8114 receives a memory read request to non-prefetchable memory space, it generates a pci express read request for 1 dword, if the system is running a 32-bit bus, and 2 dwords, if the system is running a 64-bit bus. 7.3.5.2 memory read request s to prefetchable space when the pex 8114 receives a memory read request to prefetchable memory space in pci mode, it issues a read request on the pci express interface fo r an amount of data that is determined by the prefetch register prefetch space count field (offset fa4h [13:8]) and the starting address of the request. the prefetch space count field is not used in pci-x mode because the request size is provided in the pci-x read request. use of the prefetch space count field to determine prefet ch size pertains only to pci mode. the prefetch space count field specifies the number of dwor ds to prefetch for memory reads originating on the pci bus that are forwarded to th e pci express interface. only even values between 0 and 32 are allowed. when the pex 8114 is configured as a forward bridge, prefetching occurs for all memory reads of prefetchable and non-prefetchable memory space. this occurs b ecause the bars are not used for memory reads, making it impossible to determine whether th e space is prefetchable. in reverse transparent bridge mode, prefet ching occurs only for memory r eads that address prefetchable memory space. prefetching is quad-wor d aligned, in that data is pref etched to the end of a quad-word boundary. the number of dwords prefetched is as follows: pex 8114 prefetches 2 dwords when the following conditions are met: ? prefetch space count field is cleared to 00h, and ? pci_ad0 or pci_ad1 is high ? pci_req64# is asserted (low) pex 8114 prefetches 1 dword when the following conditions are met: ? prefetch space count field is cleared to 00h, and ? pci_ad0 or pci_ad1 is high ? pci_req64# is de-asserted (high) when the prefetch space count field contains an even value gr eater than 0 and pci_ad2 is high, the number of prefetched dwords is 1 dword less than the value in the prefetch space count field; otherwise, the number of dwords prefetched is equal to the value in the prefetch space count field. only even values between 0 and 32 are allo wed. odd values provide unexpected results.
january, 2007 pci-to-pci express dis position of unused prefetched data expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 99 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.3.5.3 memory read line or memory read line multiple when the read request is a memory read line or memory read line multiple, the tlp read request size is determined by the cache line prefetch li ne count and cache line size. when a memory read line command is issued, a single cache line of data is prefetched. the number of lines pref etched for a memory read line multiple co mmand is one or two cache line s, and is controlled by the cache line prefetch line count bit (offset fa0h [4]). the cache line size is determined by the miscellaneous control register cache line size field (offset 0ch [7:0]), and can be 1, 2, 4, 8, 16, or 32 dwords. regardless of the cache line pref etch line count and cache line si ze, the prefetched tlp can never be larger than 128 bytes. the pex 8114 allows the cache line size field to be written with any value; however, if they are written to with a value other than 1, 2, 4, 8, 16 , or 32 dwords, they are treated as if the value was cleared to 0 du ring the calculation. when the cache line size field is cleared to 0, 1 dword (if the system is running a 32-bit bus) or 2 dwords (if the system is running a 64-bit bus) are prefetched. when prefetching for a given cache line size, the pr efetching is done to the end of the cache line. this means that if the starting address of the memory read line or memory read line multiple request is at the beginning of the cache line , then a full cache line of data is prefetched. if the starting address of the memory read line or memory read line multiple request is not at the beginning of the cache line, some amount of data less th an a full cache line is prefetched, such that data is prefetched up to the end of a cache line. when the read request is a memory read line multiple and the cache line prefetch line count bit is set, the bridge issues a pci express memory read tlp wi th a size such that data is prefetched up to the end of the next cache line, if the cache line size is less than or equal to 16 dwords (64 bytes). this operation is executed in an attempt to prefetch data from the pci express endpoint. if the additional data (the data requested in an attempt to prefet ch) remains unused, the bridge drops the data. 7.3.5.4 credits the pex 8114 power-on default settings in register offsets a00h , a04h , and a08h are values that advertise finite credits. 7.3.6 pci-to-pci express disposit ion of unused prefetched data after the pci express device completes the request to the pex 8114, the pex 8114 completes one of the pci device?s subsequent attempts to r ead by supplying data until the pci device: terminates the transaction normally, satisfying its need for data, ?or? depletes the data that it tran smitted from the pci express device if the pci device terminates the read, the pex 8114 flushes the remaining data it prefetched from the pci express device. if the data is depleted by th e pci device?s read, the pe x 8114 terminates the pci transaction with a disconn ect-with-data on the data phase in which the last available data is read. the pex 8114 does not store and combine data from tlps in an attempt to support lengthening the pci burst.
bridge operations plx technology, inc. 100 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.3.7 pci-to-pci express pend ing transaction count limits the pex 8114 is capable of accepting multiple posted pci writes. each write is stored in the central ram until it can be transmitted on the pci express link. non-posted transactions require completion on the pci express side of the bridge, prior to completing the transaction on the pci side of the bridge. when a non-posted transaction enters the pe x 8114, its context is saved until a pci express completion with a matching reques ter id is received. upon recei pt of the comp letion from the pci express interface, the completion is relayed to th e pci initiator, which co mpletes the transaction. the transaction is defined as outstanding from the ti me that the bridge receive s the initial pci request until the bridge completes the transaction and returns it to the pci requester. up to eight non-posted transactions can be outstanding at any given time. 7.3.8 pci-to-pci express ? pci write transaction with discontiguous byte enables pci express requires that all packet data beats, excep t the first and last, have all byte enables enabled. pci has no such requirement. if the pci data written to the pci express port disabled byte enables in the middle of a burst, the pex 81 14 continues to accept the pci data and creates two or more tlps, as necessary, to support long pci bursts, while al so honoring the pci express requirement for contiguously asserted bytes. 7.3.9 pci-to-pci express ? pc i write transactions larger than maximum packet size when a pci burst write transact ion is longer than the pci express maximum packet size, the pex 8114 creates two or more pci express tlps, as necessary, to support long bursts, while also honoring the pci express maximum packet size requir ements. when a pci data burst is completed, the tlp is transmitted and no attempt is made to combine multiple pci burst writes into a single tlp transaction. when the pex 8114 pci express lane s cannot transmit pci express tlps across the pci express interface because of posted credit depletion, which would result in th e filling of 6-kb central memory within the pex 8114, the pex 8114 starts issuing retries on the pci bus to hold-off the pci bus initiator from sending additional data to the pex 8114.
january, 2007 pci-x-to-pci express transactions expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 101 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.4 pci-x-to-pci express transactions when a pci-x device attempts a write from the pci-x bus to the pci express lanes, the pex 8114 translates pci-x burst transactions into pci express tlps. in the most basic transaction, the pex 8114 receives a data burst on the pci-x bus and transl ates the data into a pci express tlp. the pci-x protocol is more similar to pci express protocol than to pci protocol. ( that is , the pci-x transaction size is included in the request and the pci-x bus supports split responses.) these two factors allow transactions from pci-x-to-pci express to fl ow more efficiently th an transactions from pci-to-pci express. the following description of pc i-x transactions is similar to pci transactions; however, it contains a few significant differ ences, as described in the following sections. 7.4.1 pci-x-to-pci express flow control the pex 8114 ensures that the internal resources for st oring data are not overrun. if an internal data storage resource is full or approach ing full in certain cases, the pex 8114 issues retries to all new request transactions and only accep ts completions or requests to types without depleted resources. there are several data buffers that must be manage d and not allowed to overflow, including the eight pci completion buffers and internal 8-kb ram. in general, the bridge tracks the outstanding data it requested and does not transmit more requests than it has space to receive completions. there are tw o exceptions ? oversubs cribe and flood modes. in oversubscribe mode, the pex 811 4 tracks the number of outstanding bytes requested and ensures that it limits the number to that allowed in the upstream and downstream split transaction control register split transaction commitment limit fields (offsets 60h [31;16] and 64h [31;16], respectively). in flood mode, the pex 8114 accepts and forwards all read requests. 7.4.2 pci-x-to-pci express ? pci-x posted requests for posted pci-x writes, no completion information is returned to the pci-x device that originated the transaction, and when the tlp is transmitted on the pci express lin k, the transaction is considered complete. table 7-3 defines pci-x posted transactions an d the resultant pci express transactions created in response to the posted write. table 7-3. pci-x posted requests initial posted pci transactions resultant pci expr ess transaction interrupt ack not supported special cycle not supported dual address cycle fmt=01b for reads and 10b for writes memory write mwr tlp, up to maximu m packet size; type=00000b, fmt=1xb memory write block mwr tlp, up to maxi mum packet size; type=00000b, fmt=1xb
bridge operations plx technology, inc. 102 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.4.3 pci-x-to-pci express ? pci-x non-posted requests when the initial pci-x request is a non-posted wr ite, the pex 8114 complete s the pci-x transaction with a completion message, indicating a successful or unsuccessful completion following the completion from pci express. if the non-posted request is a read and the transaction data is successfully gathered, the split co mpletion is accompanied by data. when servicing non-posted pci-x transactions, the pex 8114 issues a split response to the pci-x originator when it receives the first request and cr eates and issues a non-posted tlp on the pci express link. when the pci express endpoint responds to the non-posted request with a completion, a split completion is returned to the pci-x initiator. non-posted reads return data along with the completion status. non-posted writ es return a completion with status only. there are no retries and no subsequent attempts. table 7-4 defines possible pci-x non-posted transactions and the resultant pci express transaction. note: ?x? indicates ?don?t care.? table 7-4. pci-x non-posted requests initial non-posted pci-x transactions resultant pci express transaction i/o write iowr tlp length=1; type=00000b fmt=10b i/o read iord tlp lengt h=1; type= 00000b fmt=00b memory read dword memrd tl p length=1; type=00000b fmt=0xb configuration write cfgwr0/1 tl p length=1; type=0010b fmt=10b configuration read cfgrd0/1 tl p length=1; type=0010b fmt=00b configuration type 1 write cfgwr1 tl p; length=1; type=00100b, fmt=10b configuration type 1 read cfgrd1 tlp; length=1; ty pe=00100b, fmt=00b dual address cycle fmt=01b memory read block memrd tlp length=up to maximum read request; type=00000b fmt=0xb
january, 2007 pci-x-to-pci express ? pci-x read requests larger than maximum read request size expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 103 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.4.4 pci-x-to-pci express ? pci- x read requests larger than maximum read request size during a pci-x-to-pci express read request, the pci- x read request byte count is loaded into the pci express tlp read request quantity, if the pci-x read request is less than the maximum read request size. if the read request is larger th an the pci express maximum read request size, the pex 8114 issues multiple read requests of maximum read request size or smaller, in the case of the last tlp to complete the total request size. genera tion of multiple read request tlps is performed to honor the pci express maximum read request size and contiguous byte enable requirements, while supplying the entire data quantity requested by the pci-x requester. when the data is returned from the pci express device, it is returned in tlps that are no larger than the maximum packet size, nor larger than the maximum read completion size. as tlps ar rive, they are aligned to the pci-x allowable disconnect boundary (adb), and writes with discontiguous byte enables are transmitted as completions on the pci-x bus, followed by disconnects on the adb until the original pci-x requester?s data request quantity is supplied. during long data bursts, if the pci express read co mpletion boundary (rcb) is set to 64 bytes, the bridge must combine two 64-byte pci express packets in to a single 128-byte pci-x burst, to ensure that the pci-x transfer ends on the pci-x adb boundary. the combining of the two 64-byte tlps into a single 128-byte adb is performed in parallel with transmission of the previous 128-byte burst, and is transmitted as a single 128-byte pci-x burst, thereby maximizing the pci-x bus bandwidth. the pex 8114 does not store and combine data from tlps in an attempt to support lengthening the pci burst length. 7.4.5 pci-x-to-pci express ? pci-x transfer special case this section documents the pci-x tran sfer special case that exists when pci-x write requests are larger than the maximum packet size, cross 4-kb address boundary sp aces, or have discontiguous byte enables. when a pci-x device issues write requests that are larger than the maximum packet size, if the write request burst crosses a 4-kb addr ess boundary space or the data has internal discontiguous byte enables, the pex 8114 must break up the transaction into two or more transactions, assign unique transaction ids, and store details about each transaction generated, to facilitate accounting for the transaction completion. 7.4.6 pci-x-to-pci express ? pci-x transactions that require bridge to take ownership when the pci-x transaction is broken into multiple pci express transactions, the pex 8114 must ensure that all requested data is read. to track data from large requests that require multiple tlps to generate, the pex 8114 must track all transactions to completion. the pex 8114 allows eight pci-x read request transactions to be outstanding at any time. pci-x non-posted read transactions that are smaller than the maximum read request size, as we ll as pci-x read requests that do not cross a 4-kb address boundary space, without discontiguous byte enables, are not limi ted to eight outstanding transactions. limiting the read request size, as less than or equal to the maximum read request size, allows for higher performance.
bridge operations plx technology, inc. 104 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.4.7 pci-x-to-pci express ? pci-x writes with discontiguous byte enables the pex 8114 is capable of accepting multiple posted pci-x writes. each write is stored in the central ram until it can be transmitted on the pci express link. pci express requires that all packet data beats, except the first and last, have all byte enables enab led. pci-x has no such requirement. if the pci-x data has disabled byte enables in the middle of a burst, the pex 8114 cont inues to accept the pci-x data and creates two or more tlps, as necessary, to support long pci bursts, while also honoring the pci express requirement for contiguously asserted bytes. 7.4.8 pci-x-to-pci express ? pci-x writes longer than maximum packet size when a pci-x burst transaction is longer than the pci express maximum packet size, the pex 8114 creates two or more pci express tlps, as necessary , to support long bursts, while also honoring the pci express maximum packet size requirements. when a pci-x data burst is completed, the tlp is transmitted and no attempt is made to combine multiple small pci-x burst writes into a single tlp transaction. when the pex 8114 pci express lane s cannot transmit pci express tlps across the pci express interface because of posted credit depletion, which would result in th e filling of 6-kb central memory within the pex 8114, the pex 8114 starts issuing retries on the pci bus to hold-off the pci bus initiator from sending additional data to the pex 8114.
january, 2007 pci express-to-pci transactions expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 105 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.5 pci express-to-pci transactions in pci mode, when a pci express de vice transmits a transaction from the pci express interface to the pex 8114 pci-x bus, the transaction is translated from a pci express tlp into a pci burst transaction. in the most basic transaction, th e pex 8114 receives a tlp on the pc i express lanes and translates the data into one or more pci bursts. 7.5.1 pci express-to-pci flow control credits for up to 6 kb of pci express posted an d non-posted transacti ons are issued. these transactions are queued, according to pci orderi ng transaction rules in central memory, and are transmitted to the pci-x modules as bandwidth allows, limited by the eight outstanding pci transactions. transmitting packets into the pci express side of the bridge is throttled by space remaining in the central ram. the process of transmitting transactions onto the pci bus is throttled by the number of outstanding transactions transmitted to the pci endpoints that did not complete. the pex 8114 supports up to eight outstanding transac tions on the pci bus. all transactions are driven through the bridge as quickly as possible, limited only by the pci express and pci bus bandwidths. 7.5.2 pci express-to-pci ? pci express posted transactions when servicing posted transactio ns, no completion information is returned to the pci express device that originated the transaction, a nd when the transaction is transmitted on the pci bus, the transaction is considered complete. table 7-5 defines which pci express posted transactions are supported and to which pci transaction they are translated. table 7-5. pci express posted transactions initial pci express posted transaction type resultant pci transaction memory write pci memory write. message request messages that cause changes on the pci side of the bridge are interrupt messages, which are translated to in ta#. internally, power management and error conditions can ca use error messages to generate to the pci express side of the bridge. message request with payload not supported.
bridge operations plx technology, inc. 106 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.5.3 pci express-to-pci ? pci ex press non-posted transactions when servicing non-posted pci e xpress transactions, th e pex 8114 accepts the pci express tlp and creates and issues a pci request on the pci bus. the necessary data quantity is indicated in the tlp and the pex 8114 executes as many trans actions as required on the pci bu s to write or read the requested data. after the pex 8114 successfully transmits or receives all data, it issues a completion tlp to the pci express original requester. the pex 8114 supports up to eight concurrent non-posted pci requests. table 7-6 defines the pci express non-posted requ ests and the resulting pci transactions when the non-posted pci exp ress request is received. 7.5.4 pci express-to- pci ? pci bus retry writes are serially processed on a first-come, first-served basis. reads are attempted in parallel, that is , if one request receives a disconnect, the pex 8114 attempts to gather data for another outstanding request, moving from request to request in an effort to complete as many transactions as possible, as soon as possible. if the force strong ordering bit (offset fa0h [8]) is set, after data is returned in response to a read request, the pex 8114 concentrates all requests on gathering the remaining data for that transaction until the transaction completes. by default, the bit is cleared at power-on reset. if the bit is set, only one outstanding read is allowed at a time. all posted and non-po sted write bursts on the pci bus cannot be longer than the pci express maximu m packet size. there is no internal combining of write tlps in an effort to increase the pci burst size. table 7-6. pci express non-posted transactions initial pci express non-posted transaction type resultant pci transaction i/o write request i/o write i/o read request i/o read configuration write type 0 configuration write type 0 configuration read type 0 configuration read type 0 configuration write type 1 configuration write type 1 configuration read type 1 configuration read type 1 memory read ? locked not supported ? returns a ur memory read request pci memory read, pci memory read line, or pci memory read line multiple
january, 2007 pci express-to-pci transaction request size expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 107 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.5.5 pci express-to-pci transaction request size the pex 8114 determines which type of pci read request to issue on the pci bus, based on the size of the pci express read request that the bridge rece ives. if a pci express memory read request enters the pex 8114 prefetchable memory space, with a tlp length and starting address such that all requested data is within a single cache line and is less than an entire cache line, a memory read request is issued on the pci bus. if a pci express memory read re quest enters pex 8 114 prefetchable memory space, with a tlp length great er than or equal to the cache li ne size, but less than two cache lines in size, the pex 8114 issues a memory read line request on the pci bus. when a pci express memory read request enters th e pex 8114?s prefetchable memory space, with a tlp length greater than or equal to two cache lines in size, the pe x 8114 issues a memory read line multiple request. issuing of memory read line multiple requests can be disabled by clearing the memory read line multiple enable bit. this method of determining whether to issue a memory read line or memory read line multiple request applie s only to pci mode. in pci-x mode, the transaction size is stated in the trans action and it is unnecessary to indicate the transaction size. 7.5.6 pci express-to-pci transaction completion size read completions are arranged accordi ng to the following description. if the data quantity requested in the initial pci express read request is less than or equal to the size of the maximum read completion size, the data is returned to the pci express requester in a single tlp. if the data quantity requested in the initial pci express read request is more than the maximum read completion size, or if the read crosses a 4-kb address boundary space, the completi on is constructed into more than one tlp. the tlps are sized at the maximum read completion size, except for the final tlp, which is sized to complete the remainder of the transaction.
bridge operations plx technology, inc. 108 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.6 pci express-to-pci-x transactions in pci-x mode, when a pci express device attempts a transaction from the pci express interface to the pci-x bus, the pex 8114 translates the pci express transaction tlp into a pci-x burst transaction. in the most basic transaction, the pex 8114 receives a tlp on the pci express lanes and translates the data into one or more pci-x bursts. credits fo r up to 6 kb of pci express posted and non-posted transactions are issued. these tran sactions are queued according to th e pci ordering transaction rules in central memory, and transmitted to the pci-x modules, as bandwidth allows. 7.6.1 pci express-to-pci-x posted writes for posted writes, typically including memory writes, no completion information is returned to the pci express device that origin ated the transaction, and when the tr ansaction is transmitted on the pci-x bus, the transaction is considered complete. if the pci-x bus is busy, the pex 8114 can receive and retain many posted pci express write tlps, limited only by the 6-kb central ram?s capacity. these transactions are processe d as quickly as possible , in the order received. table 7-7 defines this process. table 7-7. posted writes initial pci express posted transaction type resultant pci transaction memory write pci memory write. message request interrupt messages cause changes on the pci side of the bridge, which are translated to inta to intd. internally, power management and error conditions can cause error messages to generate to pci express side of the bridge. message request with payload not supported.
january, 2007 pci express-to-pci-x non-posted transactions expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 109 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.6.2 pci express-to-pci-x non-posted transactions in the case of non-posted pci e xpress transactions (which typi cally include memory reads and configuration and i/o writes and reads), the pe x 8114 accepts the pci express tlp and creates and issues a pci-x i/o or configuration write or read request on the pci-x bus. 7.6.2.1 non-posted writes when the transaction is a write, the pex 8114 is prepared to transfer the entire burst as a single transaction on the pci-x bus. 7.6.2.2 non-posted writes and reads when the non-posted pci express tr ansaction is a read request, th e pex 8114 issues a read request on the pci-x bus, in an effort to fulfill the pci expr ess data request. the pci-x target of the request has the option of responding with a split completion or immediate data ? the pex 8114 accepts either response: if the pci-x target responds with a split respons e, the target must complete the split response with a split completion, at least to the next adb, at a later time. if the pci-x device replies to th e pci-x read request with immedi ate data, the pci-x target must continue supplying immediate data, up to the next adb. the pex 8114 does not allow a device to respond with a single data disconnect, unless the device is prepared to respond with single data disconnects up to the next adb or to the end of the transaction, whichever comes first. this requirement is supported by the pci-x r1.0b and pci-x r2.0a . after the pex 8114 successfully transmits or receives all da ta, the pex 8114 issues a completion tlp to the pci express requester. table 7-8 defines pci express non-posted requests and the resultant pci transactions when the non-posted pci express request is received. table 7-8. non-posted writes and reads initial pci express non-posted transaction type resultant pci transaction memory read request pci-x memory re ad or memory read line multiple memory read ? locked not supported ? returns a ur i/o write request i/o write i/o read request i/o read configuration write type 0 configuration write type 0 configuration read type 0 configuration read type 0 configuration write type 1 configuration write type 1 or 0 configuration read type 1 configuration read type 1 or 0
bridge operations plx technology, inc. 110 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.6.2.3 transaction concurrency the pex 8114 supports up to eight non-posted pci e xpress requests. writes are serially processed on a first-come, first-served basis. reads are attempted in parallel, that is , if one request receives a disconnect, the pex 8114 attempts to gather data for another of the outstanding requests, moving from request to request in an effort to complete as many transactions as possible, as soon as possible. if the force strong ordering bit (offset fa0h [8]) is set, after data is returned in response to a read request, the pex 8114 concentrates all requests on gathering data to complete that transaction until the transaction completes. this is performed only if the force strong ordering bit is not set. if the bit is set, only one outstanding read is allowed at a time. all posted and non-post ed write bursts on the pci bus can be no longer than the pci express maximum packet size. there is no in ternal combining of write tlps in an effort to increase the pci burst size. read completions ar e gathered from the pci-x bus as a single dword disconnect, completions to the next adb, or completion of the entire requested data size. the completion data is collected within the pex 8114, then delivered to th e pci express requesters as tlp packets that are no larger than the maximum packet size, until all da ta requested by the pci express device is satisfied.
january, 2007 transaction transfer failures expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 111 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.7 transaction transfer failures the previously described transactio ns are the set of legal and expected transactions. successful data transfer is dependent upon the pci-x and pci exp ress devices connected to the pex 8114 performing, as described in the pci r3.0 , pci-x r2.0a , and pci express r1.0a . when a device fails to correctly perform, the transaction is likely to fail. these failures typically result in transaction timeouts and the setting of internal register bits. the pci express-to-pci/pci-x bridge r1.0 anticipates most of the typical failures and specifies error handling procedures for error condition recovery. the pex 8114 supports these error handling routines, recovers in ternal resources, and logs errors according to the specifications. for further details on error handling and recovery, refer to chapter 8, ?error handling,? and the pci express-to-pci/pci-x bridge r1.0 . the other side of this failure to flush a pending transa ction from the bridge is that it is assumed that a transaction will not complete and quickly reclaim its internal buffers. to accommodate heavy traffic densities, the bridge has several selectable trans action timeout periods. these timeout periods are based on pci_clk cycles and in pci mode, can be selected as 2 10 , 2 15 , or 2 20 clock cycles, or the timeout can be disabled. the following register bi ts are used to select these timeouts: primary discard timer ( bridge control register, offset 3ch [24]) secondary discard timer ( bridge control register, offset 3ch [25]) (discussed further in section 7.7.1 ) disable completion timeout timer (offset fa0h [5]) (discussed further in section 7.7.2 and section 7.7.4 ) enable long completion timeout timer (offset fa0h [6]) (discussed further in section 7.7.2 and section 7.7.4 ) table 7-9 defines register bit timer values as they apply to available timeouts. when completions are not returned to the pex 81 14, or when the endpoi nt does not accept returned completions held within the pex 8114, the pex 8114 internal resources remain reserved to those uncompleted transactions and cannot be used for future transactions. the following sections describe how the pex 8114 controls slow or stalled transactions: pci endpoint fails to retry read request pci-x endpoint fails to transmit split completion pci-x endpoint allows infinite retries pci express endpoint fails to return completion data note: ?x? indicates ?don?t care.? table 7-9. clock cycle timeout period selection clock cycle timeout bridge control register disable completion timeout timer (offset fa0h[5]) enable long completion timeout timer (offset fa0h[6]) primary discard timer (offset 3ch[24]) secondary discard timer (offset 3ch[25]) default0001 2 10 0000 2 15 1100 2 20 xx 0 1 no timer (disabled) xx 1 x
bridge operations plx technology, inc. 112 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.7.1 pci endpoint fails to retry read request the secondary discard timer monitors completions located within the pex 8114, waiting to return to the initial pci requester. this timer applies in pci mode, and only when the pci device initiated the initial read request. after the completion returns from the pci express endpoint to the pex 8114, if the original pci requester fails to retry for the read completion, the data remains in the pex 8114 and results in wasted resources. the timer times completions within the pex 8114. if a completion is not requested by the initial pci requester before the secondary discard timer times out, the completion is dropped and the pex 8114 reclaims the intern al resources. the timer can be configured by the bridge control register secondary discard timer bit (offset 3ch [25]) to time out at 2 10 pci_clk clock periods when set, or 2 15 pci_clk clock peri ods when cleared. 7.7.2 pci-x endpoint fails to transmit split completion when the pex 8114 receives and takes ownership of a pci express read request, and successfully forwards that request to a pci-x device and recei ves a split response, the pex 8114 waits a specified length of time for a split completion from the pci-x device. if that split completion fails to return within the specified time, the pex 8114 reclaims its internal resources. table 7-10 defines the three available timer settings, selectable by way of the enable long completion timeout timer and disable completion timeout timer bits (offset fa0h [6:5], respectively). 7.7.3 pci-x endpoint allows infinite retries when the pex 8114 attempts to master a pci or pc i-x read request transaction onto the pci-x bus in response to a pci express endpoint read request, it is expected that the pci-x endpoint might not contain data that is immediately ready and can re spond to the pex 8114?s read request with a retry. in response to the retry, the pex 8114 re-attempts th e read request, and it is expected that a future read attempt will be completed with data. if the endpoint infinitely replies to the pex 8114 read request with a retry, the pex 8114 terminates the transaction. to facilitate this, the number of retries received for each read request ar e counted. at which time , the pex 8114 compares the value stored in the maximum read cycle value field (offset fa0h [26:16]). if the number of retries received matches the number stored in the maximum read cycle value field, the read request is dropped and the retry failure status bit (offset fa0h [27]) is set. if the force strong ordering bit (offset fa0h [8]) is not set, the pex 8114 attempts up to eight read requests in a round-robin scheme. a retry count for each of the eight read requests is maintained, and co mpared, as it takes it s turn at the pci bus. table 7-10. timer settings for transmitting split completions offset fa0h[6:5] timer setting 00b 2 15 pci_clk cycles timeout 10b 2 20 pci_clk cycles timeout x1b no timeout
january, 2007 pci express endpoint fails to return completion data expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 113 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7.7.4 pci express endpoint fail s to return completion data the pex 8114 holds in ternal resources reserved to receive completions. if the pci express endpoint responsible for a completion fails to transmit a co mpletion, the pex 8114?s internal resources are at risk of remaining reserved , waiting for a completion that might never occur. the pex 8114 contains an internal timer used to trigger the bridge to reclaim internal resources reserved for completions that might never occur. table 7-11 defines the three available timer settings, selectable by way of the enable long completion timeout timer and disable completion timeout timer bits (offset fa0h [6:5], respectively). when pci non-posted requests and completions fro m pci express-to-pci are executed and no timeout is selected (offset fa0h [6:5]=x1b), the buffer holding completions for the pci requests are not automatically reclaimed. however, after 2 20 clocks transpire without a completion, the completion buffer timeout status bit for that buffer (offset f88h ) is set to indicate that the buffer is reserved for an extremely late completion. when the timeout setting is set to 2 15 or 2 20 (offset fa0h [6:5]=00b or 10b, respectively) and the completion fails to return be fore the timeout, the buffer is reclaimed after the timeout and reused. if after a tran saction times out, and the buffer is scheduled for reuse, and the pci endpoint retries the read request for the trans action that timed out, the pex 8114 returns a target abort or ffff_ffffh, as selected by the bridge control register master abort mode bit (offset 3ch [21]) to indicate that a timeout occurred to the pci endpoint. each buffer can timeout and be reclaimed three times. after three reclaims and four timeouts, the completion buffer timeout status bit for that buffer is set, to indicate th at the buffer can no longer be reclai med. when a buffer times out, if a user or operating system confirms that no stale completions are pendin g, the buffer can be re-initialized by writing 1 to the offset f88h bit representing that buffer. there is a degree of risk involved in re-initializin g buffers. if a stale completion is pending, and the software is not aware of this, and the associated completion buffer timeout status bit is mistakenly cleared, the stale completion can be mistaken for a completion to a more-recent request, resulting in incorrect data being used for the completion. if 32 pci read requests fail to complete by the pci express endpoint, all eight buffers timeout four times and all resources are consumed. to prevent a lockup condition, the pex 8114 automatically clears the completion buffer timeout status bits for all eight registers, allowi ng it to continue to accept non-posted requests. if a lockup condition occurs, the pex 8114 can no longer accept non-posted pci-x requests , which precludes configuration writes. it therefore becomes impo ssible to clear the buffer timeouts after all buffers time out. note: ?x? indicates ?don?t care.? table 7-11. timer settings for receiving completions offset fa0h[6:5] timer setting 00b 2 15 pci_clk cycles timeout 10b 2 20 pci_clk cycles timeout x1b no timeout
bridge operations plx technology, inc. 114 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 115 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 8 error handling 8.1 forward transparent bridge error handling for all errors detected by the bridge, the bridge sets the approp riate error status bit [both conventional pci/pci-x error bit(s) and pci express error status bit(s)], and generates an error message on the pci express interface, if enabled. each error condi tion has an error severity level programmable by software, and a corresponding error messa ge generated on the pci express interface. four bits control pci express in terface error message generation: pci/pci-x command register serr# enable bit pci express device control register correctable error reporting enable bit pci express device control register non-fatal error reporting enable bit pci express device control register fatal error reporting enable bit err_cor messages are enabled for transmission if the correctable error reporting enable bit is set. err_nonfatal messages are en abled for transmission if the serr# enable or non-fatal error reporting enable bit is set. err_fatal messages are enabled for transmission if the serr# enable or fatal error reporting enable bit is set. the device status register correctable error detected, non-fatal error detected , and fatal error detected status bits are set for the corresponding errors on the pci express interface, regardless of the error reporting enable bit values. 8.1.1 forward transparent bridge pci express originating interface (primary to secondary) this section describes error support for transactions that cross the bridge if the originating side is the pci express interface, and the destination inte rface is operating in conventional pci/pci-x modes. if a write request or read comple tion is received with a poisoned tlp, consider the entire data payload of the pci express transaction as corrupt . parity is inverted for all data phases when completing the transaction on the pci/pci-x bus. if a tlp is received and an ecrc error is detected, consider the entire tlp as corrupt and not forwarded, but dropped by the bridge. table 8-1 defines the translation a bridge must perf orm when forwarding a non-posted pci express request (write or read) to the pci/pci-x bus, an d the request is immediately completed on the pci/ pci-x bus, normally or with an error condition. table 8-1. translation bridge action when forwarding non-posted pci express request to pci/pci-x bus immediate pci/pci-x termination pci express completion status data transfer with parity error (non-posted writes) unsupported request data transfer with parity erro r (reads) successful (poisoned tlp) master abort unsupported request target abort completer abort
error handling plx technology, inc. 116 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.1 received poisoned tlp when the pci express interface receives a write re quest or read completion with poisoned data, the following occurs: 1. pci status register detected parity error bit is set. 2. pci status register master data parity error bit is set if the poisoned tlp is a read completion and the pci command register parity error response enable bit is set. 3. uncorrectable error status register poisoned tlp status bit is set. 4. tlp header is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register poisoned tlp error mask bit is cleared and the first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register poisoned tlp severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register poisoned tlp error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the uncorrectable error mask register poisoned tlp error mask bit is cleared and the serr# enable bit is set. 8. parity bit associated with each dword of data on the pci/pci-x bus is inverted. 9. when a poisoned tlp write request is forwarded to the pci/pci-x bus and the bridge detects pci_perr# asserted, the following occurs: ? secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set ? secondary uncorrectable error status register perr# assertion detected bit is set ? transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is clear and the first error pointer is inactive 10. no error message is generated when a poisoned tlp is forwarded to the pci/pci-x bus with inverted parity and pci_perr# is detected asserted by the pci/pci-x target device.
january, 2007 forward transparent bridge pci express originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 117 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.2 received ecrc error when a tlp is received and the bridge det ects an ecrc error, the following occurs: 1. transaction is dropped. 2. pci status register detected parity error bit is set. 3. uncorrectable error status register ecrc error status bit is set. 4. tlp header is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register ecrc error mask bit is cleared and the first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register ecrc error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register ecrc error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the uncorrectable error mask register ecrc error mask bit is cleared and the serr# enable bit is set. 8.1.1.3 pci/pci-x unco rrectable data errors the following sections describe error handlin g when forwarding non-poisoned pci express transactions to the pci/pci- x bus, and an uncorrectable pci/pci-x error is detected. posted writes when the pex 8114 detects pci_perr# asserted on the pci/pci-x secondary interface while forwarding a non-poisoned posted write tr ansaction from the pci express interface, the following occurs: 1. secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set. 2. secondary uncorrectable error status register perr# assertion detected status bit is set. 3. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable first error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the serr# enable bit is set . 7. after the error is detected, the re mainder of the data is forwarded.
error handling plx technology, inc. 118 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 non-posted writes when the pex 8114 detects pci_perr# asserted on the pci/pci-x secondary interface while forwarding a non-poisoned non-posted write transaction from the pci express interface, the following occurs: 1. secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set. 2. pci express completion with unsupported request status is generated. 3. secondary uncorrectable error status register perr# assertion detected status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the serr# enable bit is set. when the target signals split response, the bridge terminates the transaction as it would for a split request that does not contain an error and takes no fu rther action. if the returned split completion is a split completion error message, the bridge returns a pci express completion with unsupported request status to the requester.
january, 2007 forward transparent bridge pci express originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 119 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 immediate reads when the pex 8114 forwards a read request (i/o, memory, or configuration) from the pci express interface and detects an uncorrectable data error on the secondary bus while receiving an immediate or split response from the completer, the following occurs: 1. secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set. 2. secondary status register secondary detected parity error bit is set. 3. pci_perr# is asserted on the s econdary interface if the bridge control register secondary parity error response enable bit is set. 4. secondary uncorrectable error status register uncorrectable data error status bit is set. 5. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the serr# enable bit is set. after detecting an un correctable data error on the destination bus for an immediate read transaction, the pex 8114 continues to fetch data until the byte count is satisfied or the target ends the transaction. when the bridge creates the pci express completio n, it forwards the completion with successful completion and poisons the tlp. for pci-x, an unco rrectable data error on a split response does not affect handling of subsequent split completions.
error handling plx technology, inc. 120 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pci-x split read completions when the bridge forwards a non- poisoned read completion from pci express to pci-x and detects pci_perr# asserted by the pci-x target, the following occurs: 1. bridge continues to forward the remainder of the split completion. 2. secondary uncorrectable error status register perr# assertion detected status bit is set. 3. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the serr# enable bit is set. 8.1.1.4 pci/pci-x ad dress/attribute errors when the pex 8114 forwards trans actions from pci express to pci/pci-x, pci address errors are reported by serr# target assertion. when th e pex 8114 detects serr# asserted, the following occurs: 1. secondary status register secondary received system error bit is set. 2. secondary uncorrectable error status register serr# assertion detected bit is set. 3. fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable first error pointer is inactive and the secondary uncorrectable error mask register serr# assertion detected mask bit is clear. no header is logged. 4. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register serr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register serr# assertion detected mask bit is clear or the bridge control register serr# enable bit is set and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the pci command and bridge control register serr# enable bits are set .
january, 2007 forward transparent bridge pci express originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 121 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.5 pci/pci-x master abort on posted transaction when a posted write transaction fo rwarded from pci express to pci/ pci-x results in a master abort on the pci/pci-x bus, the following occurs: 1. entire transaction is discarded. 2. secondary status register secondary received master abort bit is set. 3. secondary uncorrectable error status register received master abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received master abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received master abort mask bit is cleared or the bridge control register master abort mode bit is set and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the master abort mode bit is set or the received master abort mask bit is cleared and the serr# enable bit is set. 8.1.1.6 pci/pci-x master abort on non-posted transaction when a non-posted trans action forwarded from pci express to pc i/pci-x results in a master abort on the pci/pci-x bus, the following occurs: 1. completion with unsupp orted request status is return ed on the pci express interface. 2. secondary status register secondary received master abort bit is set. 3. secondary uncorrectable error status register received master abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received master abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is genera ted on the pci express interface, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received master abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the received master abort mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 122 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.7 pci-x master a bort on split completion when a split completion forwarded from pci express to pci-x results in a master abort on the pci-x bus, the following occurs: 1. entire transaction is discarded. 2. secondary status register secondary received master abort bit is set. 3. pci-x secondary status register split completion discarded bit is set. 4. secondary uncorrectable error status register master abort on split completion status bit is set. 5. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register master abort on split completion mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register master abort on split completion severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register master abort on split completion mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the master abort on split completion mask bit is cleared and the serr# enable bit is set. 8.1.1.8 pci/pci-x target a bort on posted transaction when a posted write transaction fo rwarded from pci express to pci/pci-x results in a target abort on the pci/pci-x bus, the following occurs: 1. entire transaction is discarded. 2. secondary status register secondary received target abort bit is set. 3. secondary uncorrectable error status register received target abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received target abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received target abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the received target abort mask bit is cleared and the serr# enable bit is set.
january, 2007 forward transparent bridge pci express originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 123 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.9 pci/pci-x target a bort on non-posted transaction when a non-posted transaction forw arded from pci express to pci/pci-x results in a target abort on the pci/pci-x bus, the following occurs: 1. completion with completer a bort status is returned on the pci express interface. 2. secondary status register secondary received target abort bit is set. 3. secondary uncorrectable error status register received target abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received target abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received target abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the received target abort mask bit is cleared and the serr# enable bit is set. 8.1.1.10 pci-x target ab ort on split completion when a split completion forwarded from pci express to pci-x results in a target abort on the pci-x bus, the following occurs: 1. entire transaction is discarded. 2. secondary status register secondary received target abort bit is set. 3. pci-x secondary status register split completion discarded bit is set. 4. secondary uncorrectable error status register target abort on split completion status bit is set. 5. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register target abort on split completion mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register target abort on split completion severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register target abort on split completion mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the target abort on split completion mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 124 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.11 completer abort csr registers internal to the pex 8114 can be accessed through bar0 memory-mapped accesses. these read/write accesses are limited to single dw ord transactions. if a memory-mapped csr access is received with a tlp length field grea ter than 1 dword, the following occurs: 1. when the transaction is a write request, the transaction is dropped. when the transaction is a read request, a completion with completer abort status is returned to the requester and the pci status register signaled target abort bit is set. 2. uncorrectable error status register completer abort status bit is set. 3. tlp header is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register ecrc error mask bit is cleared and the first error pointer is inactive. 4. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register completer abort severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register completer abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the uncorrectable error mask register completer abort mask bit is cleared and the serr# enable bit is set. 8.1.1.12 unexpected completion when a completion, targeted at the bridge, is r eceived on the pci express interface that does not contain a corresponding outstanding request, the following occurs: 1. entire transaction is discarded. 2. pci-x bridge status register unexpected split completion bit is set. 3. uncorrectable error status register unexpected completion status bit is set. 4. tlp header is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register unexpected completion mask bit is cleared and the first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register unexpected completion severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register unexpected completion mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the uncorrectable error mask register unexpected completion mask bit is cleared and the serr# enable bit is set.
january, 2007 forward transparent bridge pci express originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 125 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.13 receive non-p osted request unsupported when a non-posted request, targeted to the pex 811 4, is received on the pci express interface and the bridge cannot complete the request, the following occurs: 1. completion with unsupported request completion status is returned to the requester. 2. uncorrectable error status register unsupported request error status bit is set. 3. tlp header is logged in the header log register and the advanced error capabilities and control register uncorrectable first error pointer is updated if the uncorrectable error mask register unsupported request error mask bit is cleared and the uncorrectable first error pointer is inactive. 4. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register unsupported request error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register unsupported request error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the unsupported request error mask bit is clear and the serr# enable bit is set. 8.1.1.14 link training error when a pci express link training erro r is detected, the following occurs: 1. uncorrectable error status register training error status bit is set. 2. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register training error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register training error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 3. device status register fatal error detected or non-fatal error detected bit is set. 4. pci status register signaled system error bit is set if the training error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 126 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.15 data link protocol error when a pci express data link protocol error is detected, th e following occurs: 1. uncorrectable error status register data link protocol error status bit is set. 2. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register data link protocol error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register data link protocol error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 3. device status register fatal error detected or non-fatal error detected bit is set. 4. pci status register signaled system error bit is set if the data link protocol error mask bit is clear and the serr# enable bit is set. 8.1.1.16 flow control protocol error when a pci express flow control protocol error is detected, the following occurs: 1. uncorrectable error status register flow control protocol error status bit is set. 2. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register flow control protocol error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register flow control protocol error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 3. device status register fatal error detected or non-fatal error detected bit is set. 4. pci status register signaled system error bit is set if the flow control protocol error mask bit is clear and the serr# enable bit is set.
january, 2007 forward transparent bridge pci express originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 127 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.1.17 receiver overflow when a pci express receiver overflow is detected, the following occurs: 1. uncorrectable error status register receiver overflow status bit is set. 2. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register receiver overflow severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register receiver overflow mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 3. device status register fatal error detected or non-fatal error detected bit is set. 4. pci status register signaled system error bit is set if the receiver overflow mask bit is cleared and the serr# enable bit is set. 8.1.1.18 malformed tlp when a pci express malformed tlp is received, the following occurs: 1. uncorrectable error status register malformed tlp status bit is set. 2. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register malformed tlp severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register malformed tlp mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 3. device status register fatal error detected or non-fatal error detected bit is set. 4. pci status register signaled system error bit is set if the malformed tlp mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 128 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.2 forward transparent bridge pci/pci-x originating interface (secon dary to primary) this section describes error support for transactions that cross the bridge if the originating side is the pci/pci-x bus, and the destination side is pci express. the pex 8114 supports tlp poisoning as a transmitter to permit proper forwarding of pari ty errors that occur on the pci/pci-x interface. posted write data received on the pci/pci-x interfa ce with bad parity is forw arded to the pci express interface as poisoned tlps. table 8-2 defines the error forwarding requirements fo r uncorrectable data errors that the pex 8114 detects when a transaction targets the pci express interface. table 8-3 defines the bridge behavior on a pci/pci-x de layed transaction forwarded by a bridge to the pci express interface as a memory read or i/o r ead/write request, and the pci express interface returns a completion with ur or ca status for the request. table 8-2. error forwarding requirements for uncorrectable data errors received pci/pci-x error forwarded pci express error write with parity error write request with poisoned tlp read completion or split read completion with parity error in data phase read completion with poisoned tlp configuration or i/o completion with parity error in data phase read/write completion with completer abort status split completion message with uncorrectable data error in data phase table 8-3. bridge behavior on pci/pci-x delayed transaction forwarded by bridge pci express completion status pci/pci-x immediate response master abort mode = 1 master abort mode = 0 unsupported request (on memory or i/o read) target abort normal completion, returns ffff_ffffh unsupported request (on i/o write) normal completion completer abort target abort
january, 2007 forward transparent bridge pci/pci-x originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 129 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.2.1 received pci/pci-x errors uncorrectable data error on posted write when the pex 8114 detects an un correctable data error on the pc i/pci-x secondary interface for a posted write transaction that crosse s the bridge, the following occurs: 1. pci_perr# is asserted if the bridge control register secondary parity error response enable bit is set. 2. secondary status register secondary detected parity error bit is set. 3. posted write transaction is forwarde d to pci express as a poisoned tlp. 4. pci status register master data parity error bit is set if the pci command register parity error response enable bit is set. 5. secondary uncorrectable error status register uncorrectable data error status bit is set. 6. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 7. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the uncorrectable data error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 130 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on non-posted write in conventional pci mode when a non-posted write is addressed allowing it to cross the bridge, and the pex 8114 detects an uncorrectable data error on the pc i interface, the following occurs: 1. secondary status register secondary detected parity error bit is set. 2. when the bridge control register secondary parity error response enable bit is set, the transaction is discarded and not forwar ded to the pci express interface, and pci_perr# is asserted on the pci bus. when the secondary parity error response enable bit is not set, the data is forwarded to pci express as a poisoned tlp. the pci status register master data parity error bit is set if the pci command register parity error response enable bit is set. pci_perr# is not asserted on the pci bus. 3. secondary uncorrectable error status register uncorrectable data error status bit is set. 4. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express interface, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the uncorrectable data error mask bit is clear and the serr# enable bit is set.
january, 2007 forward transparent bridge pci/pci-x originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 131 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on non-posted write in pci-x mode when a non-posted write is addressed allowing it to cross the bridge, and the pex 8114 detects an uncorrectable data error on the pc i-x interface, the following occurs: 1. secondary status register secondary detected parity error bit is set. 2. pex 8114 signals data transfer for non-posted writ e transactions, and if th ere is an uncorrectable data error, the transaction is discarded. 3. when the bridge control register secondary parity error response enable bit is set, pci_perr# is asserted on the pci-x bus. 4. secondary uncorrectable error status register uncorrectable data error status bit is set. 5. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the uncorrectable data error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 132 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on pci delayed read completions when the pex 8114 forwards a n on-poisoned read completion from pci express to pci, and it detects pci_perr# asserted by the pci master, the following occurs: 1. remainder of the completion is forwarded. 2. secondary uncorrectable error status register perr# assertion detected bit is set. 3. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the perr# assertion detected mask bit is clear and the serr# enable bit is set. when the pex 8114 forwards a poisoned read comp letion from pci express to pci, the pex 8114 proceeds with the listed actions when it detects pci_perr# asserted by the pci master; however, an error message is not generated on the pci express interface.
january, 2007 forward transparent bridge pci/pci-x originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 133 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on pci-x split read completions when the pex 8114 detects an uncorrectable da ta error on the pci-x secondary interface while receiving a split read completion that cr osses the bridge, the following occurs: 1. pci_perr# is asserted if the bridge control register secondary parity error response enable bit is set. 2. secondary status register secondary detected parity error bit is set. 3. split read completion transaction is forwarded to pci express as a poisoned tlp. 4. secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set. 5. secondary uncorrectable error status register uncorrectable data error status bit is set. 6. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 7. err_fatal/err_nonfatal message is genera ted on the pci express interface, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the uncorrectable data error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 134 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable address error when the pex 8114 detects an unco rrectable address error, and pari ty error detection is enabled by way of the bridge control register secondary parity error response enable bit, the following occurs: 1. transaction is terminated with a target abort and discarded. 2. secondary status register secondary detected parity error bit is set, independent of the bridge control register secondary parity error response enable bit value. 3. secondary status register secondary signaled target abort bit is set. 4. secondary uncorrectable error status register uncorrectable address error status bit is set. 5. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable address error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register uncorrectable address error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable address error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the uncorrectable address error mask bit is clear and the serr# enable bit is set. uncorrectable attribute error when the pex 8114 detects an uncorr ectable attribute error, and pari ty error detection is enabled by way of the bridge control register secondary parity error response enable bit, the following occurs: 1. transaction is terminated with a target abort and discarded. 2. secondary status register secondary detected parity error bit is set, independent of the bridge control register secondary parity error response enable bit value. 3. secondary status register secondary signaled target abort bit is set. 4. secondary uncorrectable error status register uncorrectable attribute error status bit is set. 5. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable attribute error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register uncorrectable attribute error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable attribute error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the uncorrectable attribute error mask bit is clear and the serr# enable bit is set.
january, 2007 forward transparent bridge pci/pci-x originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 135 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.2.2 unsupported request (ur) completion status the pex 8114 provides two methods for handl ing a pci express completion received with unsupported request (ur) status in response to re quests originated by the pci/pci-x interface. the bridge control register master abort mode bit controls the respons e. in either case, the pci status register received master abort bit is set. master abort mode bit cleared this is the default pci compatibility mode, and an unsupported request is not considered an error. when a read transaction initiated on the pci/pci-x bus results in the return of a completion with unsupported request status, the pex 8114 returns fff f_ffffh to the originating master and asserts pci_trdy# to terminate the read transaction normally on the originating interface. when a non-posted write transaction results in a completion with unsupported request status, the pex 8114 asserts pci_trdy# to complete the write tr ansaction normally on th e originating bus, and discards the write data. master abort mode bit set when the master abort mode bit is set, the pex 8114 signals a ta rget abort to the originating master of an upstream read or non-post ed write transaction when the co rresponding request on the pci express interface results in a completion with ur status. additionally, the secondary status register secondary signaled target abort bit is set. 8.1.2.3 completer abort (ca) completion status when the pex 8114 receives a completion with comp leter abort status on the pci express primary interface in response to a forwarded no n-posted pci/pci-x transaction, the pci status register received target abort bit is set. a ca response results in a delayed transaction target abort or a split completion target abort error message on the pci/pci-x bus. the pex 8114 provides data to the requesting pci/pci-x agent, up to the point where data was successful ly returned from the pci express interface, then signals target abort. the secondary status register secondary signaled target abort bit is set when signaling targ et abort to a pci/pci-x agent.
error handling plx technology, inc. 136 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.2.4 split completion errors split completion messag e with completer errors a transaction originating from the pci express interface and requ iring a completion can be forwarded to the pci-x interface, where the target (complet er) responds with split response. if the completer encounters a condition that prevents the successful execution of a split transaction, the completer must notify the requester of the abnormal condition, by returning a split completion message with the completer error class. if the bridge responds with completer abort status, it sets the pci status register signaled target abort bit. table 8-4 defines the abnormal conditions and the bridge?s response to the split completion message. each is described in th e sections that follow. table 8-4. abnormal conditions and bridge response to split completion messages pci-x split completion message completer error code bit set in secondary status register bit set in secondary uncorrectable error status register pci express completion status class index master abort 1h 00h received master abort received master abort unsupported request target abort 1h 01h received target abort received target abort completer abort uncorrectable write data error 1h 02h master data parity error perr# assertion detected unsupported request byte count out of range 2h 00h none none unsupported request uncorrectable split write data error 2h 01h master data parity error perr# assertion detected unsupported request device-specific error 2h 8xh none none completer abort
january, 2007 forward transparent bridge pci/pci-x originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 137 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 split completion message with master abort when a bridge receives a split completion message indicating master abor t, the following occurs: 1. completion with unsupported request status is returned to the requester. 2. secondary status register received master abort bit is set. 3. secondary uncorrectable error status register received master abort status bit is set. 4. tlp header of the original request is logged in the secondary header log register and the fech register secondary uncorrectab le error pointer is updated if the secondary uncorrectable error mask register received master abort mask bit is clear and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received master abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the received master abort mask bit is cleared and the serr# enable bit is set. split completion message with target abort when a bridge receives a split completion message indicating target abort, the following occurs: 1. completion with completer abort status is returned to the requester. 2. secondary status register received target abort bit is set. 3. secondary uncorrectable error status register received target abort status bit is set. 4. pci status register signaled target abort bit is set. 5. tlp header of the original request is logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received target abort mask bit is clear and the secondary uncorrectable first error pointer is inactive. 6. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received target abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the received target abort mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 138 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 split completion message with uncorrectable write data error or uncorrectable split write data error when a bridge receives a split completion messag e indicating an uncorrect able write data error or uncorrectable split write data error, the following occurs: 1. completion with unsupported request status is returned to the requester. 2. secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set. 3. secondary uncorrectable error status register perr# assertion detected bit is set. 4. tlp header of the original request is logged in the secondary header log register and the fech register secondary uncorrectab le error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. err_fatal/err_nonfatal message is genera ted on the pci express interface, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the perr# assertion detected mask bit is clear and the serr# enable bit is set. split completion message with byte count out of range when a bridge receives a split completion message indicating a by te count out of range error, a completion with unsupported request status is returned to the requester. split completion message with device-specific error when a bridge receives a split completion message indicating a device-speci fic error, a completion with completer abort status is returned to the requester.
january, 2007 forward transparent bridge pci/pci-x originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 139 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 corrupted or unexpected split completion when a bridge receives a corrupted or unexp ected split completion, the following occurs: 1. pci-x secondary status register unexpected split completion status bit is set. 2. secondary uncorrectable error status register unexpected split completion error status bit is set. 3. tlp header of the corrupt or unexpected split completion is logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register unexpected split completion mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register unexpected split co mpletion severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register unexpected split completion mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the unexpected split completion mask bit is clear and the serr# enable bit is set. data parity error on split completion messages when a bridge detects a data error during th e data phase of a split completion message, the following occurs: 1. secondary uncorrectable error status register uncorrectable split completion message data error status bit is set. 2. tlp header of the split completion is logged in the secondary header log register and the fech register secondary uncorrectab le error pointer is updated if the secondary uncorrectable error mask register uncorrectable split completion message data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 3. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register uncorrectable split completion message data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable split completion message data error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the uncorrectable split completion message data error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 140 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.3 forward transparent bridge timeout errors 8.1.3.1 pci express completion timeout errors the pci express completion timeout mechanism allows requesters to abort a no n-posted request if a completion does not arrive within a reasonable time. bridges, when acting as initiators on the pci express interface on behalf of internally genera ted requests, or when forwarding requests from a secondary interface, behave as endpoints for requests of which they assume ownership. if a completion timeout is detected and the link is up, the pex 8114 responds as if a completion with unsupported request status was received, and the following occurs: 1. uncorrectable error status register completion timeout status bit is set. 2. tlp header of the original request is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register completion timeout mask bit is cleared and the first error pointer is inactive. 3. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the uncorrectable error severity register completion timeout error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register completion timeout mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the serr# enable bit is set. 8.1.3.2 pci delayed transaction timeout errors the pex 8114 contains delayed transaction discar d timers for each queued delayed transaction. if a delayed transaction timeout is detected, the following occurs: 1. bridge control register discard timer status bit and secondary uncorrectable error status register delayed transaction discard timer expired status bit are set. 2. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the secondary uncorrectable error severity register delayed transaction discard timer expired severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register delayed transaction discard timer expired mask bit is cleared or bridge control register discard timer serr# enable bit is set and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 3. device status register fatal error detected or non-fatal error detected bit is set. 4. pci status register signaled system error bit is set if the serr# enable bit is set.
january, 2007 forward transparent bridge serr# forwarding expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 141 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.1.4 forward transparent bridge serr# forwarding pci devices can assert serr# when detecting erro rs that compromise system integrity. when the pex 8114 detects serr# asserted on the seco ndary pci/pci-x bus, the following occurs: 1. secondary status register received system error bit and secondary uncorrectable error status register serr# assertion detected status bit are set. 2. err_fatal/err_nonfatal message is generate d on the pci express in terface, depending on the severity of the secondary uncorrectable error severity register serr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register serr# assertion detected mask bit is clear or bridge control register serr# enable bit is set and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set 3. device status register fatal error detected or non-fatal error detected bit is set. 4. pci status register signaled system error bit is set if the pci command and bridge control register serr# enable bits are set.
error handling plx technology, inc. 142 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2 reverse transparent bridge error handling 8.2.1 reverse transparent bridge forwarding pex 8114 system errors and system error messages pci express error reporting messages are not compat ible with pci/pci-x interfaces. there are three types of error levels, each report ed by a unique error message: correctable (err_cor) non-fatal (err_nonfatal) fatal (err_fatal) error messages received from the pci express hierarchy are forwarded upstream, through the pci_inta# or pci_serr# balls or a message signaled interrupt (msi). to control error reporting and forwarding by the pex 8114, use one of the following: root port registers conventional pci type 1 register set for all errors detected by the bridge, the bridge sets the approp riate error status bit [both conventional pci/pci-x error bit(s) and pci express error status bit(s)]. if reporting for an error is not masked, the bridge also reports to the root port registers. the root port registers forwar d bridge-detected errors in the same manner as error messages received from the hierarchy, as if the brid ge transmitted an error message to itself.
january, 2007 reverse transparent bridge forwarding pex 8114 system errors and system error messages expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 143 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.1.1 root port erro r forwarding control the root port registers provide c ontrol, to enable forwarding of each error type, independently of the others. the root control register enables reporting of error events through conventional pci system errors. pci_serr# is asserted when the pex 8114 detects er rors that are not masked, or an error message is received and the corresponding reporting enable bit is set. three bits control pci_serr# assertion for correctable, non-fatal, and fatal errors: system error on correctable error enable system error on non-fatal error enable system error on fatal error enable the root error command register enables forwar ding of error events through interrupt requests: pci_inta# is asserted when the pex 8114 detects errors that are not masked, the corresponding reporting enable bit is set, and the command register interrupt disable bit is cleared an msi is transmitted, and pci_inta# is not asse rted, when the pex 8114 de tects errors that are not masked, the corresponding reporting enable bit is set, the command register interrupt disable bit is cleared, and the msi control register msi enable bit is set pci_inta# is asserted when the pex 8114 receives an error message on the pci express interface, and the corresponding reporting enable bit is set an msi is transmitted, and pci_inta# is not asserted, when the pex 8114 receives an error message on the pci express interface, the corresponding reporting enable bit is set, and the msi control register msi enable bit is set three root error command register bits control pci_inta# assertion or msi signaling for correctable, non-fatal, and fatal errors: correctable error reporting enable non-fatal error reporting enable fatal error reporting enable
error handling plx technology, inc. 144 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.1.2 conventional pci type 1 error forwarding control two conventional pci bits control reporting and fo rwarding of bridge-detect ed errors and error messages received from the pci express hierarchy: pci command register serr# enable bit bridge control register serr# enable bit fatal and non-fatal errors detected by th e bridge are forwarded to the host by pci_serr# assertion, if the pci command register serr# enable bit is set. fatal and non-fatal error messages received from the pci express hierarchy are forwarded to the host by pci_serr# assertion if the pci command and bridge control register serr# enable bits are set. 8.2.1.3 bridge-detect ed error reporting errors detected by the pex 8114 that are not mask ed must be enabled to report to the root port registers. the following four bits control error reporting to the root port registers: pci command register serr# enable bit pci express device control register correctable error reporting enable bit pci express device control register non-fatal error reporting enable bit pci express device control register fatal error reporting enable bit additionally, the serr# enable bit controls the forwarding of errors upstream to the host. correctable errors (err_cor) are reported to the root port registers if the correctable error reporting enable bit is set. non-fatal errors (err_nonfatal) are reported to the root port registers if the serr# enable or non-fatal error reporting enable bit is set. fatal errors (err_fatal) are reported to the root port registers if the serr# enable or fatal error reporting enable bit is set. the device status register correctable , non-fatal , and fatal error detected status bits are set for the corresponding errors, regardless of the error reporting enable settings.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 145 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2 reverse transparent brid ge pci express originating interface (secondary to primary) this section describes error support for transactions that cross the bridge if the originating side is the pci express (secondary) interface, and the destination interface is operating in a conventional pci/ pci-x (primary) mode. if a write request or read completion is received wi th a poisoned tlp, the entire pci express transaction da ta payload must be considered corrupt . parity is inverted for all data phases when completing pci/pci-x bus transactions. if a tlp is received and an ecrc error is detected, the entire tlp must be considered corr upt and not forwarded, but dropped by the bridge. table 8-5 defines the translation the pex 8114 performs when it forwards a non-posted pci express request (write or read) to the pci/pci-x bus, a nd the request is immediately completed normally on the pci/pci-x bus or w ith an error condition. table 8-5. translation bridge action when forwarding non-posted pci express request to pci/pci-x bus immediate pci/pci-x termination pci express comp letion status data transfer with parity error (reads) successful (poisoned tlp) completion with parity error (non- posted writes) unsupported request master abort unsupported request target abort completer abort
error handling plx technology, inc. 146 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.1 received poisoned tlp when a write request or read co mpletion is received by the pci express interface, and the data is poisoned, the following occurs: 1. secondary status register secondary detected parity error bit is set. 2. secondary status register secondary master data parity error bit is set if the poisoned tlp is a read completion and the bridge control register secondary parity error response enable bit is set. 3. uncorrectable error status register poisoned tlp status bit is set. 4. tlp header is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register poisoned tlp error mask bit is cleared and the first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register poisoned tlp severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register poisoned tlp error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the poisoned tlp severity 6. pci_inta# is asserted on the pci/pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register poisoned tlp severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register poisoned tlp error mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the poisoned tlp severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the poisoned tlp severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the uncorrectable error mask register poisoned tlp error mask bit is cleared and the serr# enable bit is set. 9. parity bit associated with each dword of data on the pci/pci-x bus is inverted. 10. when a poisoned tlp write request is forwarded to the pci/pci-x bus and the bridge detects pci_perr# asserted, the following occurs: ?pci status register master data parity error bit is set if the pci command register parity error response enable bit is set ? secondary uncorrectable error status register perr# assertion detected bit is set ? transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the first error pointer is inactive
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 147 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.2 received ecrc error when a tlp is received and the bridge det ects an ecrc error, the following occurs: 1. transaction is dropped. 2. secondary status register secondary detected parity error bit is set. 3. uncorrectable error status register ecrc error status bit is set. 4. tlp header is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register ecrc error mask bit is cleared and the first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register ecrc error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register ecrc error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the ecrc error severity 6. pci_inta# is asserted on the pci/pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register ecrc error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register ecrc error mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the ecrc error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the ecrc error severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the ecrc error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 148 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.3 pci/pci-x unco rrectable data errors the following sections describe error handling when forwarding non-poisoned pci express transactions to the pci/pci- x bus, and an uncorrectable pci/pci-x error is detected. posted writes when the pex 8114 detects pci_perr# asserted on the pci/pci-x pr imary interface while forwarding a non-poisoned posted write trans action from the pci express in terface, the following occurs: 1. pci status register master data parity error bit is set if the pci command register parity error response enable bit is set. 2. secondary uncorrectable error status register perr# assertion detected status bit is set. 3. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the perr# assertion detected severity 5. pci_inta# is asserted on the pci/pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the perr# assertion detected mask bit is clear and the serr# enable bit is set. 8. after the error is detected, the re mainder of the data is forwarded.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 149 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 non-posted writes when the pex 8114 detects pci_perr# asserted on the pci/pci-x pr imary interface while forwarding a non-poisoned non-posted write tr ansaction from the pci express interface, the following occurs: 1. pci status register master data parity error bit is set if the pci command register parity error response enable bit is set. 2. pci express completion with unsupported request status is generated. 3. secondary uncorrectable error status register perr# assertion detected status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the perr# assertion detected severity 6. pci_inta# is asserted on the pci/pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the perr# assertion detected mask bit is clear and the serr# enable bit is set. when the target signals split response, the bridge terminates the transaction as it would for a split request that does not contain an error and takes no fu rther action. if the returned split completion is a split completion error message, the bridge returns a pci express completion with unsupported request status to the requester.
error handling plx technology, inc. 150 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 immediate reads when the pex 8114 forwards a read request (i/o, memory, or configuration) from the pci express interface and detects an uncorrectable data error on the primary bus while re ceiving an immediate or split response from the completer, the following occurs: 1. pci status register master data parity error bit is set if the pci command register parity error response enable bit is set. 2. pci status register detected parity error bit is set. 3. pci_perr# is asserted on the s econdary interface if the pci command register parity error response enable bit is set. 4. secondary uncorrectable error status register uncorrectable data error status bit is set. 5. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable data error severity 7. pci_inta# is asserted on the pci/pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the uncorrectable data error mask bit is clear and the serr# enable bit is set. after detecting an un correctable data error on the destination bus for an immediate read transaction, the pex 8114 continues to fetch data until the byte count is satisfied or the target ends the transaction. when the bridge creates the pci express completio n, it forwards the completion with successful completion status and poisons the tlp. for pci-x, an uncorrectable data error on a split response does not affect handling of subsequent split completions.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 151 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pci-x split read completions when the bridge forwards a non- poisoned read completion from pci express to pci-x and detects pci_perr# asserted by the pci-x target, the following occurs: 1. bridge continues to forward the remainder of the split completion. 2. secondary uncorrectable error status register perr# assertion detected status bit is set. 3. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. pci_serr# is asserted on the pci-x bus, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the perr# assertion detected severity 5. pci_inta# is asserted on the pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the perr# assertion detected mask bit is clear and the serr# enable bit is set.
error handling plx technology, inc. 152 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.4 pci/pci-x ad dress/attribute errors when the pex 8114 forwards trans actions from pci express to pci/pci-x, the target asserts serr# to report pci address errors. the pex 8114 ignores the serr# assertion, and allows the pci central resource to service the error. 8.2.2.5 pci/pci-x master abort on posted transaction when a posted write transaction fo rwarded from pci express to pci/ pci-x results in a master abort on the pci/pci-x bus, the following occurs: 1. entire transaction is discarded. 2. pci status register received master abort bit is set. 3. secondary uncorrectable error status register received master abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received master abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received master abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the received master abort severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register received master abort mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received master abort severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received master abort severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the received master abort mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 153 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.6 pci/pci-x master abort on non-posted transaction when a non-posted trans action forwarded from pci express to pc i/pci-x results in a master abort on the pci/pci-x bus, the following occurs: 1. completion with unsupp orted request status is return ed on the pci express interface. 2. pci status register received master abort bit is set. 3. secondary uncorrectable error status register received master abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received master abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received master abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the received master abort severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register received master abort mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received master abort severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received master abort severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the received master abort mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 154 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.7 pci-x master a bort on split completion when a split completion forwarded from pci express to pci-x results in a master abort on the pci-x bus, the following occurs: 1. entire transaction is discarded. 2. pci status register received master abort bit is set. 3. pci-x status register split completion discarded bit is set. 4. secondary uncorrectable error status register master abort on split completion status bit is set. 5. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register master abort on split completion mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. pci_serr# is asserted on the pci-x bus, depending on the secondary uncorrectable error severity register master abort on split completion severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register master abort on split completion mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the master abort on split completion severity 7. pci_inta# is asserted on the pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register master abort on split completion severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register master abort on split completion mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the master abort on split completion severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the master abort on split completion severity 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the master abort on split completion mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 155 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.8 pci/pci-x target a bort on posted transaction when a posted write transaction fo rwarded from pci express to pci/pci-x results in a target abort on the pci/pci-x bus, the following occurs: 1. entire transaction is discarded. 2. pci status register received target abort bit is set. 3. secondary uncorrectable error status register received target abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received target abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received target abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the received target abort severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register received target abort mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received target abort severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received target abort severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the received target abort mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 156 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.9 pci/pci-x target a bort on non-posted transaction when a non-posted transaction forw arded from pci express to pci/pci-x results in a target abort on the pci/pci-x bus, the following occurs: 1. completion with completer a bort status is returned on the pci express interface. 2. pci status register received target abort bit is set. 3. secondary uncorrectable error status register received target abort status bit is set. 4. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received target abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received target abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the received target abort severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register received target abort mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received target abort severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received target abort severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the received target abort mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 157 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.10 pci-x target ab ort on split completion when a split completion forwarded from pci express to pci-x results in a target abort on the pci-x bus, the following occurs: 1. entire transaction is discarded. 2. pci status register received target abort bit is set. 3. pci-x bridge status register split completion discarded bit is set. 4. secondary uncorrectable error status register target abort on split completion status bit is set. 5. transaction command, attributes , and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register target abort on split completion mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register target abort on split completion severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register target abort on split completion mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the target abort on split completion severity 7. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register target abort on split completion severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register target abort on split completion mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the target abort on split completion severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the target abort on split completion severity 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the target abort on split completion mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 158 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.11 unexpected completion received when a completion targeted at the bridge is received on the pc i express interface, without a corresponding outstanding request, the following occurs: 1. entire transaction is discarded. 2. pci-x secondary status register unexpected split completion bit is set. 3. uncorrectable error status register unexpected completion status bit is set. 4. tlp header is logged in the header log register and the advanced error capabilities and control register uncorrectable first error pointer is updated if the uncorrectable error mask register unexpected co mpletion mask bit is cleared and the uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register unexpected completion severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register unexpected completion mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the unexpected completion severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register unexpected completion severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register unexpected completion mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the unexpected completion severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the unexpected completion severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the unexpected co mpletion mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 159 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.12 received request unsupported when a non-posted request, targeted to the pex 811 4, is received on the pci express interface and the bridge cannot complete the request, the following occurs: 1. completion with unsupported request completion status is returned to the requester. 2. uncorrectable error status register unsupported request error status bit is set. 3. tlp header is logged in the header log register and the advanced error capabilities and control register uncorrectable first error pointer is updated if the uncorrectable error mask register unsupported request error mask bit is cleared and the uncorrectable first error pointer is inactive. 4. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register unsupported request error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register unsupported request error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the unsupported request error severity 5. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register unsupported request error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register unsupported request error mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the unsupported request error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the unsupported request error severity 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the unsupported request error mask bit is clear and the serr# enable bit is set.
error handling plx technology, inc. 160 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.13 link training error when a pci express link training erro r is detected, the following occurs: 1. uncorrectable error status register training error status bit is set. 2. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register training error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register training error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the training error severity 3. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register training error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register training error mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the training error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the training error severity 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the training error mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 161 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.14 data link protocol error when a pci express data link protocol error is detected, th e following occurs: 1. uncorrectable error status register data link protocol error status bit is set. 2. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register data link protocol error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register data link protocol error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the data link protocol error severity 3. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register data link protocol error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register data link protocol error mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the data link protocol error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the data link protocol error severity 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the data link protocol error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 162 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.15 flow control protocol error when a pci express flow control protocol error is detected, the following occurs: 1. uncorrectable error status register flow control protocol error status bit is set. 2. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register flow control protocol error severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register flow control protocol error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the flow control protocol error severity 3. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register flow control protocol error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register flow control protocol error mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the flow control protocol error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the flow control protocol error severity 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the flow control protocol error mask bit is clear and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci express originating interface (secondary to primary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 163 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.16 receiver overflow when a pci express receiver overflow is detected, the following occurs: 1. uncorrectable error status register receiver overflow status bit is set. 2. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register receiver overflow severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register receiver overflow mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the receiver overflow severity 3. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register receiver overflow severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register receiver overflow mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the receiver overflow severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the receiver overflow severity 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the receiver overflow mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 164 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.2.17 malformed tlp when a pci express malformed tlp is received, the following occurs: 1. uncorrectable error status register malformed tlp status bit is set. 2. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register malformed tlp severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register malformed tlp mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the malformed tlp severity 3. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register malformed tlp severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register malformed tlp mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the malformed tlp severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the malformed tlp severity 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the malformed tlp mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 165 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.3 reverse transparent bridge pci/pci-x originating interface (primary to secondary) this section describes error support for transactions that cross the bridge if the originating side is the pci/pci-x bus, and the destination side is pc i express. the pex 8114 supports tlp poisoning as a transmitter to allow proper forwarding of pari ty errors that occur on the pci/pci-x interface. posted write data received on the pci/pci-x interface with bad parity is forwarded to the pci express interface as poisoned tlps. table 8-6 defines the error forwarding requirements fo r uncorrectable data errors that the pex 8114 detects when a transaction ta rgets the pci express interface. table 8-7 defines the bridge behavior on a pci/pci-x delayed transaction forwarded by the pex 8114 to the pci express interface as a memory read or i/o read/write request, and the pci express interface returns a completion with ur or ca status for the request. table 8-6. error forwarding requirements for uncorrectable data errors received pci/pci-x error forwarded pci express error write with parity error write request with poisoned tlp read completion or split read completion with parity error in data phase read completion with poisoned tlp configuration or i/o completion with parity error in data phase read/write completion with completer abort status split completion message with uncorrectable data error in data phase table 8-7. bridge behavior on pci/pci-x delayed transaction forwarded by pex 8114 pci express completion status pci/pci-x immediate response master abort mode = 1 master abort mode = 0 unsupported request (on memory or i/o read) target abort normal completion, returns ffff_ffffh unsupported request (on i/o write) normal completion completer abort target abort
error handling plx technology, inc. 166 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.3.1 received pci/pci-x errors uncorrectable data error on posted write when the pex 8114 detects an un correctable data error on the pc i/pci-x primary interface for a posted write transaction that crosse s the bridge, the following occurs: 1. pci_perr# is asserted if the pci command register parity error response enable bit is set. 2. pci status register detected parity error bit is set. 3. posted write transaction is forwarded to the pci express interface as a poisoned tlp. 4. secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set. 5. secondary uncorrectable error status register uncorrectable data error status bit is set. 6. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 7. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable data error severity 8. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity 9. device status register fatal error detected or non-fatal error detected bit is set. 10. pci status register signaled system error bit is set if the uncorrectable data error mask bit is clear and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 167 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on non-posted write in conventional pci mode when a non-posted write is addressed allowing it to cross the bridge, and the pex 8114 detects an uncorrectable data error on the pc i interface, the following occurs: 1. pci status register detected parity error bit is set. 2. when the pci command register parity error response enable bit is set, the transaction is discarded and not forwarded to the pci express interface. pci_perr# is asserted on the pci bus. when the parity error response enable bit is not set, the data is forwarded to the pci express interface as a poisoned tlp. the secondary status register secondary master data parity error bit is set if the bridge control register secondary parity error response enable bit is set. pci_perr# is not asserted on the pci bus. 3. secondary uncorrectable error status register uncorrectable data error status bit is set. 4. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable data error severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the uncorrectable data error mask bit is clear and the serr# enable bit is set.
error handling plx technology, inc. 168 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on non-posted write in pci-x mode when a non-posted write is addressed allowing it to cross the bridge, and the pex 8114 detects an uncorrectable data error on the pc i-x interface, the following occurs: 1. pci status register detected parity error bit is set. 2. pex 8114 signals a data transfer for non-posted wr ite transactions. if ther e is an uncorrectable data error, the transaction is discarded. 3. when the pci command register parity error response enable bit is set, pci_perr# is asserted on the pci-x bus. 4. secondary uncorrectable error status register uncorrectable data error status bit is set. 5. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. pci_serr# is asserted on the pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable data error severity 7. pci_inta# is asserted on the pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the uncorrectable data error mask bit is clear and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 169 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on pci delayed read completions when the pex 8114 forwards a non- poisoned or poisoned read completion from pci express to pci, and it detects pci_perr# asserted by the pci master, the following occurs: 1. remainder of the completion is forwarded. 2. secondary uncorrectable error status register perr# assertion detected bit is set. 3. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. pci_serr# is asserted on the pci bus, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register perr# assertion detected mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the perr# assertion detected severity 5. pci_inta# is asserted on the pci bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register perr# assertion detected mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the perr# assertion detected mask bit is clear and the serr# enable bit is set. if the pex 8114 forwards a poisoned read completion from pci express to pci, the pex 8114 proceeds with the above ac tions when it detects pci_perr# asserted by the pci master; however, an error message is not generated on the pci express interface.
error handling plx technology, inc. 170 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable data error on pci-x split read completions when the pex 8114 detects an uncorrectable data error on the pci-x interface while receiving a split read completion that crosses the bridge, the following occurs: 1. pci_perr# is asserted if the pci command register parity error response enable bit is set. 2. pci status register detected parity error bit is set. 3. split read completion tr ansaction is forwarded to the pci express interface as a poisoned tlp. 4. pci status register master data parity error bit is set if the pci command register parity error response enable bit is set. 5. secondary uncorrectable error status register uncorrectable data error status bit is set. 6. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 7. pci_serr# is asserted on the pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable data error severity 8. pci_inta# is asserted on the pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable data error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable data error mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable data error severity 9. device status register fatal error detected or non-fatal error detected bit is set. 10. pci status register signaled system error bit is set if the uncorrectable data error mask bit is clear and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 171 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable address error when the pex 8114 detects an unco rrectable address error and parity error detection is enabled by way of the pci command register parity error response enable bit, the following occurs: 1. transaction is terminated with a target abort and discarded. 2. pci status register detected parity error bit is set, independent of the pci command register parity error response enable bit value. 3. pci status register signaled target abort bit is set. 4. secondary uncorrectable error status register uncorrectable address error status bit is set. 5. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable address error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable address error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable address error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable address error severity 7. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable address error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable address error mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable address error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable address error severity 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the uncorrectable address error mask bit is clear and the serr# enable bit is set.
error handling plx technology, inc. 172 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 uncorrectable attribute error when the pex 8114 detects an unco rrectable attribute erro r and parity error detection is enabled by way of the pci command register parity error response enable bit, the following occurs: 1. transaction is terminated with a target abort and discarded. 2. pci status register detected parity error bit is set, independent of the pci command register parity error response enable bit value. 3. pci status register signaled target abort bit is set. 4. secondary uncorrectable error status register uncorrectable attribute error status bit is set. 5. transaction command, attributes, and address are logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable attribute error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable attribute error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable attribute error mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable attribute error severity 7. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable attribute error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable attribute error mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable attribute error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable attribute error severity 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the uncorrectable attribute error mask bit is clear and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 173 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.3.2 unsupported request (ur) completion status the pex 8114 provides two methods for handl ing a pci express completion received with unsupported request (ur) status in response to a request originated by the pci/pci-x interface. the bridge control register master abort mode bit controls the respon se. in either case, the secondary status register secondary received master abort bit is set. master abort mode bit cleared this is the default pci/pci-x compatibility mode, an d a ur is not considered an error. when a read transaction initiated on the pci/pci-x bus results in the return of a completion with ur status, the pex 8114 returns ffff_ffffh to the originating master and asserts pci_trdy# to terminate the read transaction normally on the originating interf ace. when a non-posted wr ite transaction results in a completion with ur status, the pex 8114 assert s pci_trdy# to complete the write transaction normally on the originating bus and discards the write data. master abort mode bit set when the master abort mode bit is set, the pex 8114 signals a ta rget abort to the originating master of an upstream read or non-post ed write transaction when the co rresponding request on the pci express interface results in a completion with ur status. additionally, the pci status register signaled target abort bit is set. 8.2.3.3 completer ab ort completion status when the pex 8114 receives a completion with co mpleter abort (ca) status on the pci express secondary interface, in response to a forwar ded non-posted pci/pci-x transaction, the secondary status register secondary received target abort bit is set. a ca response results in a delayed transaction target abort or split completion target abort error message on the pci/pci-x bus. the pex 8114 provides data to the reque sting pci/pci-x agent, up to the point wher e data was successfully returned from the pci express interf ace, then signals target abort. the pci status register signaled target abort bit is set when signaling targ et abort to a pci/pci-x agent.
error handling plx technology, inc. 174 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.3.4 split completion errors split completion messag e with completer errors a transaction originating from the pci express interface and requ iring a completion can be forwarded to the pci-x interface where the target (completer ) responds with split response. if the completer encounters a condition that prevents the successful execution of a split transaction, the completer must notify the requester of the abnormal condition by returning a split completion message with the completer error class. if the bridge responds with completer abort status, it sets the secondary status register signaled target abort bit. table 8-8 defines the abnormal conditions and the bridge?s response to the split completion message. each is described in th e sections that follow. table 8-8. abnormal conditions and bridge response to split completion messages pci-x split completion message completer error code bit set in pci status register bit set in secondary uncorrectable error status register pci express completion status class index master abort 1h 00h received master abort received master abort unsupported request target abort 1h 01h received target abort received target abort completer abort uncorrectable write data error 1h 02h master data parity error perr# assertion detected unsupported request byte count out of range 2h 00h none none unsupported request uncorrectable split write data error 2h 01h master data parity error perr# assertion detected unsupported request device-specific error 2h 8xh none none completer abort
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 175 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 split completion message with master abort when a bridge receives a split completion message indicating master abor t, the following occurs: 1. completion with unsupported request status is returned to the requester. 2. pci status register received master abort bit is set. 3. secondary uncorrectable error status register received master abort status bit is set. 4. tlp header of the original request is logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received master abort status mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received master abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the received master abort severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register received master abort severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register received master abort mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received master abort severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received master abort severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the received master abort mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 176 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 split completion message with target abort when a bridge receives a split completion message indicating target abort, the following occurs: 1. completion with completer abort status is returned to the requester. 2. pci status register received target abort bit is set. 3. secondary uncorrectable error status register received target abort bit is set. 4. secondary status register signaled target abort bit is set. 5. tlp header of the original request is logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register received target abort mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 6. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register received target abort mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the received target abort severity 7. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register received target abort severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register received target abort mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received target abort severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the received target abort severity 8. device status register fatal error detected or non-fatal error detected bit is set. 9. pci status register signaled system error bit is set if the received target abort mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 177 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 split completion message with uncorrectable write data error or uncorrectable split write data error when a bridge receives a split co mpletion message indica ting an uncorrectable write data error or uncorrectable split write data error, the following occurs: 1. completion with unsupported request status is returned to the requester. 2. pci status register master data parity error bit is set if the pci command register parity error response enable bit is set. 3. secondary uncorrectable error status register perr# assertion detected bit is set. 4. tlp header of the original request is logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register perr# assertion detected mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 5. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the perr# assertion detected severity 6. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register perr# assertion detected severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register perr# assertion detected mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the perr# assertion detected severity 7. device status register fatal error detected or non-fatal error detected bit is set. 8. pci status register signaled system error bit is set if the perr# assertion detected mask bit is clear and the serr# enable bit is set. split completion message with byte count out of range when a bridge receives a split completion message indicating a by te count out of range error, a completion with unsupported request status is returned to the requester. split completion message with device-specific error when a bridge receives a split completion message indicating a device-speci fic error, a completion with completer abort status is returned to the requester.
error handling plx technology, inc. 178 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 corrupted or unexpected split completion when a bridge receives a corrupted or unexp ected split completion, the following occurs: 1. pci-x bridge status register unexpected split completion status bit is set. 2. secondary uncorrectable error status register unexpected split completion error status bit is set. 3. tlp header of the corrupt or unexpected split completion is logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register unexpected split completion mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 4. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register unexpected split completion severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register unexpected split completion mask bit is clear and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the unexpected split completion severity 5. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register unexpected split completion severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register unexpected split completion mask bit is clear and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the unexpected split completion severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the unexpected split completion severity 6. device status register fatal error detected or non-fatal error detected bit is set. 7. pci status register signaled system error bit is set if the unexpected split completion mask bit is clear and the serr# enable bit is set.
january, 2007 reverse transparent bridge pci/pci-x originating interface (primary to secondary) expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 179 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 data parity error on split completion messages when a bridge detects a data error during the da ta phase of a split completion message, the following occurs: 1. secondary uncorrectable error status register uncorrectable split completion message data error status bit is set. 2. tlp header of the split completion is logged in the secondary header log register and the fech register secondary uncorrectable error pointer is updated if the secondary uncorrectable error mask register uncorrectable split completion message data error mask bit is cleared and the secondary uncorrectable first error pointer is inactive. 3. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register uncorrectable split completion message data error severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register uncorrectable split completion message data error mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the uncorrectable split completion message data error severity 4. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the secondary uncorrectable error severity register uncorrectable split completion message data error severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? secondary uncorrectable error mask register uncorrectable split completion message data error mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable split completion message data error severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the uncorrectable split completion message data error severity 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the uncorrectable split completion message data error mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 180 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.4 reverse transparent bridge timeout errors 8.2.4.1 pci express completion timeout errors the pci express completion timeout mechanism allows requesters to abort a no n-posted request if a completion does not arrive within a reasonable time. bridges, when acting as initiators on the pci express interface on behalf of in ternally generated requests or when forwarding requests from a secondary interface, behave as endpoints for requests of which they assume ownership. if a completion timeout is detected and the link is up, the pex 8114 responds as if a completion with unsupported request status was received, and the following occurs: 1. uncorrectable error status register completion timeout status bit is set. 2. tlp header of the original request is logged in the header log register and the advanced error capabilities and control register first error pointer is updated if the uncorrectable error mask register completion timeout mask bit is cleared and the first error pointer is inactive. 3. pci_serr# is asserted on the pci/pci-x bus, depending on the secondary uncorrectable error severity register completion timeout severity bit?s severity, if the following conditions are met: ? secondary uncorrectable error mask register completion timeout mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the completion timeout severity 4. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register completion timeout severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register completion timeout mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the completion timeout severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the completion timeout severity 5. device status register fatal error detected or non-fatal error detected bit is set. 6. pci status register signaled system error bit is set if the completion timeout mask bit is cleared and the serr# enable bit is set.
january, 2007 reverse transparent bridge timeout errors expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 181 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.4.2 pci delayed transaction timeout errors the pex 8114 has delayed transaction discard time rs for each queued delayed transaction. if a delayed transaction timeout is detected, the following occurs: 1. bridge control register discard timer status bit and secondary uncorrectable error status register delayed transaction discard timer expired status bit are set. 2. pci_serr# is asserted on the pci/pci-x bus, depending on the uncorrectable error severity register delayed transaction discard timer expired severity bit?s severity, if the following conditions are met: ? uncorrectable error mask register delayed transaction discard timer expired mask bit is cleared and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set, the root control register system error on fatal error enable or system error on non-fatal error enable bit is set, and both bits match the delayed transaction discard timer expired severity 3. pci_inta# is asserted on the pci/pci-x bu s ?or? an msi is transmitted if the msi control register msi enable bit is set, depending on the uncorrectable error severity register delayed transaction discard timer expired severity bit?s severity, if the following conditions are met: ? command register interrupt disable bit is cleared and ? uncorrectable error mask register delayed transaction discard timer expired mask bit is cleared and ? root error command register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the delayed transaction discard timer expired severity and either ?pci command register serr# enable bit is set or ? pci express device control register fatal error reporting enable or non-fatal error reporting enable bit is set and matches the delayed transaction discard timer expired severity 4. device status register fatal error detected or non-fatal error detected bit is set. 5. pci status register signaled system error bit is set if the delayed transaction discard timer expired mask bit is cleared and the serr# enable bit is set.
error handling plx technology, inc. 182 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8.2.5 reverse transparent bridge pci express error messages pci express devices can transmit error messages wh en detecting errors th at compromise system integrity. when the pex 8114 r eceives error messages on the secondary pci express interface, the following occurs: 1. secondary status register received system error bit is set if a non-fatal (err_nonfatal) or fatal (err_fatal) error message is received. 2. pci_serr# is asserted on the pci/pci-x bus when one of the following conditions occur: ?root control register system error on correctable error enable bit is set and a correctable error message (err_cor) is received ?root control register system error on non-fatal error enable bit is set and a non-fatal error message (err_nonfatal) is received ?root control register system error on fatal error enable bit is set and a fatal error message (err_fatal) is received ?pci command and bridge control register serr# enable bits are set and a non-fatal error message (err_nonfatal) is received ?pci command and bridge control register serr# enable bits are set and a fatal error message (err_fatal) is received 3. pci_inta# is asserted on the pci/pci-x bus ?or? an msi is transmitted if the msi control register msi enable bit is set, when one of the following conditions occur: ? root error command register correctable error reporting enable bit is set and a correctable error message (err_cor) is received ? root error command register non-fatal error reporting enable bit is set and a non-fatal error message (err_nonfatal) is received ? root error command register fatal error reporting enable bit is set and a fatal error message (err_fatal) is received
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 183 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 9 serial eeprom 9.1 introduction the on-bridge serial eeprom controller is contai ned in the pex 8114 pci/pci-x port, as illustrated in figure 9-1 . the controller performs a serial eeprom download when: a serial eeprom is present, as indicated by the ee_pr# strap ball = low, and the configuration registers are reset to their default values. figure 9-1. serial eeprom connections to pex 8114 initialization serial eeprom port serial eeprom controller pci/pci-x port port ee_pr# ee_cs# ee_do ee_di ee_sk pex 8114 configuration data pci express port
serial eeprom plx technology, inc. 184 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 9.2 configuration data download the serial eeprom controller generates an ee_sk signal by dividing the pci_clk by 16, resulting in a shift clock frequency up to 8.3 mhz. the serial eeprom controller reads a total of 1,004 bytes, from the serial eeprom, which represents all data necessary to initialize the pex 8114 registers. the serial eeprom memory map reflects th e basic device register map. a de tailed description of the serial eeprom memory maps is provided in appendix a, ?serial eeprom map.? note: for a pci-x clock greater than 66 mhz, a 10-mhz serial eeprom is needed. for clock rates of 66 mhz and lower, a 5-mhz serial eeprom is sufficient. when registers are modified throug h the serial eeprom load, the seri al eeprom must retain data for all registers. registers that must be modified away from their power-on default states can be changed by loading the necessary modified valu es in the serial eeprom, at the location that corresponds to that register?s value in the serial eeprom map. register s that are not intended to be modified from their default values by the serial eeprom load must be located within the serial eeprom loaded with the default value. serial peripheral interface eeproms, from 1 kb up to 64 kb sizes, are supported. a minimum of a 1-kb serial eeprom is required to support the pex 8114 register load. if a serial eeprom larger than 1 kb is used, the additional space remains unu sed by the pex 8114 regist er load resources and is used as a general-purpose serial eeprom. the regist er load data starts at location 0 in the serial eeprom and the serial eeprom data is loaded into the registers, in ascending sequence, and mapped according to the register assignment tables in appendix a, ?serial eeprom map.? the table is arranged with the left column listing the configur ation space register (csr) addresses and the right column listing the serial eeprom address to load to modify the csr. in a few instances, the value of a single pci-defi ned or plx-specific csr must be stored in two separate internal registers within the pex 8114. when writing a csr using pci-type configuration writes ? memory-mapped writes or pointer indirect writes ? the internal st ate machines associated with the write, place the data in both internal registers, without intervention. when loading a csr location that contains two internal copies of the re gister using serial eeprom loads, the value must be specifically loaded into both internal registers ( that is , two distinct writes to two distinct locations are required). therefore, in certain instances, when creating the seri al eeprom image, the value needed in a csr must be placed in two address locations in th e serial eeprom, allowing two distinct writes to occur. the required registers for this procedure ar e indicated in the regist er assignment tables in appendix a, ?serial eeprom map,? by having two serial eeprom addresses listed in a row that has only one corresponding csr address. in cases where two serial eeprom addresses must be loaded to modify one csr location, the data load ed into both serial eeprom addresses must be identical or the pex 8114?s operation is undefined. during the serial eeprom download , the controller checks for a valid class code and terminates the download if a value other than 060400h is used. while downloading data, the pex 8114 generates a crc value from the data read. when the serial eeprom download is completed, the generated crc value is compared to a crc value stored in the last dword location of the serial eeprom. for seri al eeproms, the crc value is located at serial eeprom byte offset 03ech. all crc are calculated in dwords and the crc value is also a dword. the crc is calculated, starting at location 0, and is calculated th rough one location below where the crc is stored. the crc polynomial is as follows: g(x) = x 32 + x 31 + x 30 + x 28 + x 27 + x 25 + x 24 + x 22 + x 21 + x 20 + x 16 + x 10 + x 9 + x 6 + 1 a c code sample used to generate the crc is provided in appendix b, ?sample c code implementation of crc generator.?
january, 2007 configuration data download expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 185 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 when the crc values match, the pex 8114 sets the serial eeprom status and control register serial eeprom present [17:16] value to 01b (serial eeprom download complete and serial eeprom crc check is correct). when the crc check fails, the pex 8114 sets all the registers for the po rt to their default values, and sets the serial eeprom present [17:16] bits to 11b to indicate failure. disable the crc check by loading a value of 1 in serial eeprom status register crc disable bit (offset 260h [21]) during the serial eeprom load. it is the responsibility of system software to detect that the serial eeprom download is completed without error. serial eeprom register initiali zation data, as well as user-acces sible, general-purpose space located above the register initialization data, can be modi fied by writes to the pex 8114 plx-specific serial eeprom registers. the serial eeprom status and control register (offset 260h ) contains status and control bits that set the read/write address and cau se status data to be written to or read from the serial eeprom. there are 14 addr ess bits ? bits [12:0] and extended address bit 20. the addressing is at a dword address (rather than a byte offset), whic h allows 16-kb dwords or 64 kb to be addressed. the serial eeprom buffer register (offset 264h ) contains data to be written to, or the most recent data read from, the seri al eeprom. (refer to register 14-73 and register 14-74 , respectively, for further details.)
serial eeprom plx technology, inc. 186 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 187 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 10 interrupt handler 10.1 introduction the pex 8114 includes two types of interrupts: conventional pci interrupt, pci/pci-x pci_int[d:a]# , which are pex 8114 i/o balls on the pci/pci-x bus and their analogous pci express assert_int x virtual interrupt messages message signal interrupt (msi), which is conveyed with memory write transactions in forward transparent bridge mode, conventional pc i interrupts generated external to the bridge and asserted on the bridge int x balls, when enabled, are converted by the pex 8114 to virtual interrupt messages and transmitted upstream on the pci express interface. msi interrupts are passed through the pex 8114 from pci/pci-x to pci express. interrupts generated by sources internal to the bridge can be converted to msi interrupt messages or assert_inta. in reverse transparent bridge mode, the virt ual interrupt messages received on the pci express interface are converted to conventional pci interrup t signals and driven on the pci_int[d:a]# balls. msi interrupts are passed through the pex 8114, from pci express to pci/pci-x. interrupts generated by sources internal to the bridge can be converted to msi interrupt or assert_inta and deassert_inta messages. 10.2 interrupt handler features interrupt handler feat ures are as follows: senses internal interrupt events generates virtual interrupt messages from conventional pci pci_int[d:a]# balls drives conventional pci_int[d:a]# balls from virtual interrupt messages signals interrupts through virtual inta# signa ling, pci_int[d:a]# signal conventional pci assertion, or msi
interrupt handler plx technology, inc. 188 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 10.3 events that cause interrupts events internal to the pex 8114 th at cause interrupts are as follows: hot plug events ? attention button pressed ? power fault detected ? mrl sensor changed ? presence detect changed ? command completed internal error fifo overflow power management events pci express egress credit update timeout interrupts can also be generated if the root error command register (offset f94h ), is implemented by software in reverse transparent bridge mode. conditions that cause these interrupts are as follows: correctable error message is received by the pex 8114 from downstream and the root error command register correctable error reporting enable bit is set (offset f94h[0]=1) non-fatal error message is received by the pex 8114 from downstream and the root error command register non-fatal error reporting enable bit is set (offset f94h[1]=1) fatal error message is received by the pex 8114 from do wnstream and the root error command register fatal error reporting enable bit is set (offset f94h[2]=1) correctable error is detect ed by the pex 8114, the command register interrupt disable bit is not set, and the root error command register correctable error reporting enable bit is set (offset 04h [10]=0 and offset f94h[0]=1, respectively) non-fatal error is detected by the pex 8114, the command register interrupt disable bit is not set and the root error command register non-fatal error reporting enable bit is set (offset 04h[10]=0 and offset f94h[1]=1, respectively) fatal error is detected by the pex 8114 the is not set in the command register interrupt disable bit is not set and the root error command register fatal error reporting enable bit is set (offset 04h[10]=0 and offset f94h[2]=1, respectively) interrupt requests proceed to the inte rrupt generator module, which sets the status register interrupt status bit. setting the status bit causes an inta# interrupt or msi to generate, depending on which interrupt is enabled. inta# and msi interrupt genera tion are mutually exclusive.
january, 2007 intx# signaling expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 189 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 10.4 int x # signaling in forward transparent bridge mode, the pex 8114 converts pci_int x # ball interrupts to virtual pci express int x # signaled interrupts. pci/pci-x interrupts appearing on pci_int x # lines are converted to pci express-comp atible packets (assert_int x # and deassert_int x # signaled interrupts) and transmitted to the upstream port. in reverse transparent bridge mode, th e pex 8114 converts pci express virtual int x # signaled interrupts to pci_int x # interrupts. assert_int x # and deassert_int x # signaled interrupts from the pci express port are converted to the pci_int x # ball interrupts. the pex 8114 supports the pci r3.0 interrupt pin and interrupt line registers (offset 3ch [15:8 and 7:0], respectively), as well as the pci r3.0 command register interrupt disable and status register interrupt status bits (offset 04h [10, 19], respectively). although the pci express r1.0a provides int[d:a]# for pci_int[d:a]# interrupt signaling, the pex 8114 uses only pci_inta# for internal interrupt message generation. when msi is disabled ( message signaled interrupt control register msi enable bit is cleared to 0) and inta#-type interrupts are not disabled ( command register interrupt disable bit value is 0), interrupt requests from a defined ev ent generate inta#-type interrupts. when msi is enabled, the interrupt requests from a defined event generate msi type interrupts, regardless of the command register interrupt disable bit state. when pci_inta# interrupts are enabled and there is an interrupt request from interrupt sources internal to the pex 8114, the status register interrupt status bit is set. in forward transparent bridge mode, when the interrupt status bit is set by an interrupt source internal to the pex 8114, an assert_inta# messa ge is transmitted on the pci express interface. when an external pci-x device asserts the int x # input to the pex 8114, the interrupt status bit is not set; however, the assert_int x # message is translated. when the external pci-x device later de-asserts the pci_int x # input, the deassert_int x # message is transmitted without action from the host software. in reverse transparent bridge mode, when the iinterrupt status bit is set, the pci_inta# signal is asserted on the pci/pci-x bus. when an interrupt source internal to the pex 8114 causes an interrupt to be transmitted to the pci express root complex, the host so ftware reads and clears the event st atus after servicing the interrupt. when an interrupt source in ternal to the pex 8114 causes an interrupt, the pci device hardware clears the status register interrupt status bit when all event stat us bits are cleared, and transmits a deassert_inta# message on the pci e xpress interface or de-asserts pci_inta# on the pci/pci-x bus.
interrupt handler plx technology, inc. 190 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 10.5 message signaled interrupts (msi) a scheme supported by pex 8114 is the msi, which is optional for pci r3.0 devices, but required for pci express devices. the msi method uses memory wr ite transactions to deliver interrupts. msi are edge-triggered interrupts. if msi is enabled and the interrupt status bit is set, the module generates an msi. msi and int[d:a]# interrupt gene ration are mutually exclusive. 10.5.1 msi capability structure table 10-1 defines the message capability structure required for msi, and is implemented in the interrupt generator module. the capability pointer register (defined in the pci r3.0 ) contains the pointer to the capability id . the message address , message upper address , and message data registers are located at offsets capability pointer + 4h, capability pointer + 8h, and capability pointer + ch, respectively. table 10-1. message signaled interrupt capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 message signaled interrupt control next capability pointer ( 58h if pci-x; 68h if pci express) capability id ( 05h ) 48h lower message address[31:0] 4ch upper message address[63:32] 50h reserved message data 54h
january, 2007 msi operation expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 191 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 10.5.2 msi operation at configuration, system software traverses the capability list of the function. if a capability id of 05h is found, the function implements msi. system software reads the message signaled interrupt capability list register to determine whether the pex 8114 is set up to support msi. because the pex 8114 supports only one message for msi, the multiple message enable and msi 64-bit address capable fields are always 000b. system software initializes the msi 64-bit address capable field. when set, the message address field is 64 bits when not set, the message address field is 32 bits system software initializes the message data register (offset 54h ) with a system-specified message. the msi enable bit is cleared after reset and software must set the bit if the system supports the msi scheme. after the bit is enabled, the module perfor ms a dword memory write to the address specified by the message address register contents. the two lower bytes of data written are taken from the contents of the two lower bytes of the message data register. the upper two bytes of data are zero (0). because the multiple message enable field is always 000b, the module is not permitted to change the low order bits of message data to indicate a multiple message vector, and all message data register data bits are directly copied to the data. after the interrupt status bit is set and a message generated, the module does not generate another message until the system services the interrupt and clears the event status bits. the module hardware clears the interrupt status bit when all event status bits are cleared. 10.6 remapping inta# interrupts the pex 8114 does not perform interrupt remapping, due to its single internal register-set topology. when the pex 8114 acts as a forward bridge, interrupt lines inta_ intb_, intc_, and intd_ are routed straight through the pex 8114 and converted in to de-assert interrupt and assert interrupt a, b, c, and d packets, respectively, on the pci express side of the bridge. when pex 8114 acts as a reverse bridge, each assert a, b, c, and d interrupt and de-assert interrupt packet causes the interrupt a, b, c, and d li nes, respectively, to assert and de-assert. refer to the pci express-to-pci/pci-x bridge r1.0 , section 8.2, for an explanation of routing for option a bridges.
interrupt handler plx technology, inc. 192 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 193 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 11 pci/pci-x arbiter 11.1 introduction the pci/pci-x arbiter effi ciently manages accesses to the pci/pci- x bus shared by multiple masters. it is not required that all systems provide equal bus access to all masters. in reality, most systems require certain masters be granted greater access to the bus than others. this is the case for systems with an embedded processor. it is assumed that the bus access requirements for all masters in a system are known. it is possible to program the bus access requiremen ts to meet system needs. 11.2 arbiter key features the key features of the pci/ pci-x arbiter are as follows: arbiter supports up to five pci-x or conventional pci devices (four external and one internal) bus allocation is programmable in 10% increments park bus on latest master enable/disable arbiter (by way of strap_arb ball) address stepping on configuration cycles asserts grants in two ways: ? standard pci/pci-x-compliant grants during accesses ? wait for idle bus to issue grant
pci/pci-x arbiter plx technology, inc. 194 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 11.3 functional block diagram at any time, more than one pci/pci-x bus master can assert its specific pci_req[3:0]# signal and request pci/pci-x bus ownership. the arbiter de termines which pci/pci-x devices acquire bus ownership by asserting the specific device pci_gnt[3:0]# signal. figure 11-1 illustrates the relationship between the pci/pci-x devices and pci/pci-x arbiter. figure 11-1. internal pci arbiter top-level diagram internal pci arbiter pci_rst# pci_clk pci_irdy# pci_frame# strap_arb pci/pci-x device 0 pci_gnt0# pci_req0# pci/pci-x device 1 pci_gnt1# pci_req1# pci/pci-x device 2 pci_gnt2# pci_req2# pci/pci-x device 3 pci_gnt3# pci_req3#
january, 2007 pex 8114 arbiter usage expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 195 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 11.4 pex 8114 arbiter usage figure 11-2 illustrates pci/pci-x arbiter use in a pex 8114 application. in this illustration, four request/grant pairs are used only when the arbiter is enabled. another active request/grant pair is shown, regardless of whether the arbiter is enable d. the pair interfaces with the external arbiter as pci_req# when the arbiter is disabled. the pair acts as pci_req0# when the arbiter is enabled. figure 11-2. pex 8114 internal pci arbiter usage internal pci arbiter gntn3 gntn2 gntn1 reqn1 reqn2 reqn3 gntn4 reqn4 gntn0 reqn0 0 1 reqn_int gntn_int reqn0_in gntn0_out pex 8114 strap_arb reqn_out gntn_in strap_arb strapping ball reqn1_in gntn1_out reqn2_in gntn2_out reqn3_in gntn3_out
pci/pci-x arbiter plx technology, inc. 196 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 11.5 external bus functional description the pci/pci-x arbiter is designed to arbitrate the bu s requests of up to four pci/pci-x master devices on the pci/pci-x bus. the pci-x bus includes seve ral enhancements that enable faster and more efficient data transfers than the pci local bus allo wed, at pci-x bus clock frequencies up to 133 mhz. because of these higher clock rate s, register all inputs and outputs. registering request signals by the arbiter should in no way limit its usage to pci-x bus applications. it is backward-compatible with the pci bus and functions as an ar biter in the pci environment. note: registering of an arbiter signal is performed in compliance to the pci-x r2.0a . no additional requirements are implied herein. 11.6 detailed functional description arbitration is necessary if more than one mast er simultaneously requests the bus. when only one master is requesting the bus and the bus is idle, the requesting bus receives the grant if it is allowed at least one configuration register a ssignment. the pex 8114 can be config ured as a slave to an external arbiter, or function as the pci bus arbiter supporti ng up to four external pci bus requesters and the pex 8114?s internal request. the pci arbiter registers (offsets fa8h , fach , and fb0h ), in conjunction with the strap_arb ball, control pex 8114 arbitration characteristics. when strap_arb is grounded, the pex 8114 functions as a slave to the external arbiter. when functioning as a slave to the exte rnal arbiter, the pex 8114 requests access to the pci bus by asserting pci_req# , and receives grants from th e external arbiter on the pci_gnt# ball. the three pci arbiter registers are divided into ten, three-bit arbiter allocation subregisters. when the arbiter is enabled, the pci bus bandwidth is distributed in 10% increments, by loading the allocation subregisters with the value that represents an external or internal arbitration contender. table 11-1 defines the bandwidth allocations that o ccur when one of the 10 arbiter allocation subregisters are set or cleared to the values listed. it is not required that the requester values be evenly distributed in the allocation subregisters to achieve the proper bus percentage, or to achieve random bu s allocation. the register power-on default values provide equal bandwidth distribution among the requesters. typically, the arbiter allocation subregisters are set at initialization; however, they can be modified at any time. if the value representing a request ball is not loaded into an arbitration allocation subregister, that reques ter is not granted access to the pci bus. if all arbitrati on allocation subregisters are loaded with the same requester id, all pci bus bandwidth is allocated to that requester. table 11-1. arbiter allocation subregister values and bandwidth allocation arbiter allocation subregister value bandwidth allocation 000b allocates 10% of the bus bandw idth to the internal requests. 001b allocates 10% of the bus ba ndwidth to the pci_req0# input. 010b allocates 10% of the bus ba ndwidth to the pci_req1# input. 011b allocates 10% of the bus ba ndwidth to the pci_req2# input. 100b allocates 10% of the bus ba ndwidth to the pci_req3# input. 101b and higher effectively removes that arbi ter allocation subregister from the set of usable registers ( for example , if five of the arbiter allocation s ubregisters are loaded with 111b, each of the remaining five allocation subregisters represent 20% of the bus bandwidth).
january, 2007 bus parking expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 197 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 11.6.1 bus parking the arbiter is designed to implement bus parking when there are no pending requests (bus idle). in this case, the arbiter allows the grant signal for the last ma ster to remain active. this ensures that if the last master requested the bus again, it receives an immedi ate grant; however, if another master requests the bus, the arbiter causes all grants to go high before issuing a new grant. 11.6.2 hidden bus arbitration the pci r3.0 allows bus arbitration to occur while the currently granted device is performing a data transfer. this feature greatly re duces arbitration overhead and improves bus utilization. hidden arbitration occurs if the control re gister grant_mode has a value of 1; otherwise, arbitration occurs when the bus is idle. idle bus arbitration supports conventional pci devices. 11.6.3 address stepping the pex 8114?s internal pci arbiter supports address stepping. to acquire maximum pci bus utilization, the arbiter removes a gr ant from a device that requests the bu s if it fails to start a transaction on the bus within a specified minimum number of pci_clk cycles. in pci-x mode high-frequency operation, when severa l devices are connected to the high-order address lines, the ad bus can be slow to sett le when a device is trying to driv e a configuration cycle on the bus. to accommodate these slow transitions during c onfigurations, a configuring master can delay pci_frame# assertion one extra cycle, to allow the ad bus lines sufficient time to settle. the pci_frame# delayed assertion is called address stepping . when a configuring master delays pci_frame# assertion, if the master is used with a high-performance arbite r, the arbiter can remove the grant signal when the configuring master star ts to assert pci_frame#. address stepping forces the arbiter to allow one extra clock cycle for the device that is driving the configuration to assert pci_frame# before removing the grant. the address stepping enable bit (offset fa0h [13]) controls pex 8114 address stepping. at reset, the bit is cleared to 0 and address st epping is disabled. setting the address stepping enable bit causes the arbiter to delay grant removal during pci-x configuration cycles.
pci/pci-x arbiter plx technology, inc. 198 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 199 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 12 hot plug support 12.1 hot plug purpose and capabilities note: the pex 8114?s hot plug controller is compliant with the hot plug r1.0 and pci standard hot plug controller and subsystem r1.0. hot plug capabilities allow orderly insertion and extraction of boards from a running system, without adversely affecting the system. board insertion or extraction, without system down time, is performed when repair of a faulty board or system reconfiguration becomes n ecessary. hot plug capabilities also allow systems to isolate faulty boards in the ev ent of a failure. the pe x 8114 includes a hot plug controller capable of supporting hot plugging of a downstream pci express link. therefore, the hot plug controller is used when the pex 8114 is in reverse transparent bridge mode. pci/pci-x hot plug is not supported. do not use the pex 8114 to support hot plug in forward transparent bridge mode. 12.1.1 hot plug controller capabilities insertion and removal of pci express boards, without removing system power hot plug controller function board present and mrl sensor signal support power indicator and attention indicator output signal controlled attention button monitored power fault detection and faulty board isolation power switch for controlling downstream device power generates pme for a hot plug event in a sleeping system (d3hot) presence detect is achieved through an in -band serdes receiver detect mechanism or by the hp_prsnt# signal
hot plug support plx technology, inc. 200 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 12.1.2 hot plug port external signals the pex 8114 hot plug controller includes nine hot plug signals. these signals are detailed in table 12-1 . the signal ball numbers are provided in table 2-5, ?hot plug signals (9 balls).? table 12-1. hot plug signals signal name type description hp_atnled# o hot plug attention led slot control logic output used to driv e the attention indicator. set low to turn on the led. high/off = standard operation low/on = operational problem at this slot blinking = slot is identified at the user?s request blinking frequency = 2.0 hz, 50% duty cycle hp_button# i pu hot plug attention button slot control logic input directly connected to th e attention button, which can be pressed to request hot plug operations. can be implemented on the bridge or on the downstream device. hp_clken# o clock enable reference clock enable output. enabled when the slot capabilities register power controller present bit is set (offset 7ch[1]=1), and controlled by the slot control register power controller control bit (offset 80h[10]). the time delay from hp_pwren# (a nd hp_pwrled#) output assertion to hp_clken# output assertion is pr ogrammable from 16 ms (default) to 128 ms, in the hpc tpepv delay field (offset 1e0h[4:3]). hp_mrl# i pu manually operated retention latch sensor slot control logic and power controll er input directly connected to the mrl sensor. manually operated retent ion latch switch si gnal for inserting and extracting hot plug-capable boards. high = board is not available or properly seated in slot low = board properly seated in slot hp_perst# o reset hot plug reset for downstream link. enabled by the slot control register power controller control bit (offset 80h[10]). hp_prsnt# i pu pci present input connected to external logic th at outputs prsnt# directly from the external combination of prsnt1# and prsnt2#. hp_pwren# o power enable slot control logic output that controls the slot power state. when hp_pwren# is low, power is enabled to the slot. hp_pwrflt# i pu power fault input indicates that the power controller for the slot detected a power fault on one or more supply rails. hp_pwrled# o power led slot control logic output used to dr ive the power indicator. this output is set low to turn on the led.
january, 2007 hot plug typical hardware configuration expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 201 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 12.1.3 hot plug typical hardware configuration figure 12-1 illustrates a typical system-level hardware configuration using the pex 8114 to provide hot plug support in reverse transparent bridge mode. figure 12-1. hot plug typical hardware configuration for reverse transparent bridge mode application pex 8114 reverse bridge pci host pci_pme# or inta# hot plug hp_button# hp_mrl# hp_pwrflt# hp_prsnt# hp_atnled# hp_pwrled# hp_pwren# hp_clken# hot plug controller hot plug express add-in board attention button manually operated retention latch (mrl) attention led power led power fault pci express device hp_perst#
hot plug support plx technology, inc. 202 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 12.1.4 hot plug se quence illustration the following scenarios define the hot plug sequences for removing and installing boards. to remove a board: 1. determine that the board must be removed and notify the pci host by pressing the attention button or typing a command on the host console. 2. the hot plug portion of the operating system quies ces the appropriate boar d driver and blinks the attention led. 3. the hot plug system driver asserts hp_perst# , powers down the slot by way of hp_pwren# de-assertion, and turns off the power led, indicating that the board can be removed. 4. disengages the mrl switch and allows the board to be removed. 5. the hot plug driver de tects the mrl switch disconnect, and the hp_prsnt# lines indicate that no board is present. to insert a board: 1. insert the board and notify the system console, mrl, or attention button. 2. the system tells the hot plug driver to power-up the slot, de-assert hp_perst#, and turn on the power led. 3. the hot plug driver indicates to the sy stem that the boar d is ready for use. 12.1.5 pci express capabilities register the hot plug configuration, capabilities, command, status, and events are included in the pex 8114 pci express capabilities register. the app licable register map is provided in table 12-2 . 12.1.6 hot plug interrupts the hot plug controller supports hot plug interrupt generation on the following events: ? attention button pressed ? power fault detected ? mrl sensor changed ? presence detect changed ? command completed depending on the pex 8114 downstream pci express port power state, a hot plug event can generate a system interrupt or pme. when the pex 8114 down stream pci express port is in the d0 power state, hot plug events generate a system interrupt; when not in the d0 state, a pme interrupt is generated on hot plug events. the command completed bit does not generate a pme interrupt. when the system is in sleep mode, hot plug operation cause s a system wakeup using pme logic. table 12-2. pci express capabilities register map (partial) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 slot capabilities (reverse tr ansparent bridge mode only) 7ch slot status slot control 80h
january, 2007 hot plug insertion and removal process expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 203 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 12.1.7 hot plug insert ion and removal process table 12-3 defines the board insertion pro cedure supported by the pex 8114. table 12-4 defines the board removal procedure. table 12-3. hot plug insertion process operator hot plug controller software a. place board in slot. 1. presence detect state bit is set to 1. 2. presence detect change bit is set to 1. 3. pci_inta# is asserted, if enabled. 4. pci_inta# is de-asserted. presence detect change bit is cleared to 0. b. lock the mrl (manually operated retention latch). 5. mrl sensor present bit is cleared to 0. 6. mrl sensor change d bit is set to 1. 7. pci_inta# is asserted, if enabled. 8. pci_inta# is de-asserted. mrl sensor change d bit is cleared to 0. c. press attention button. 9. attention button present bit is set to 1. 10. pci_inta# is asserted, if enabled. 11. pci_inta# is de-asserted. attention button present bit is cleared to 0. d. power indicator blinks. 12. power indicator control field is set to 10b. 13. power indicator blink message is transmitted downstream. 14. command complete bit is set to 1. 15. pci_inta# is asserted, if enabled. 16. pci_inta# is de-asserted. write to power indicator control field to blink the power led, to indicate that the board is being powered up. command complete bit is cleared to 0. e. power indicator on. 17. power indicator control field is set to 01b. 18. after a t pepv delay of 16 ms, command complete bit is set. 19. pci_inta# is asserted, if enabled. 20. pci_inta# is de-asserted. write to the control register power indicator control field, to turn on power to the port. command complete bit is cleared to 0.
hot plug support plx technology, inc. 204 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 table 12-4. hot plug removal process operator hot plug controller software a. press attention button. 1. attention button present bit is set to 1. 2. pci_inta# is asserted, if enabled. if the attention button is present on the downstream device, the ?attention button? message is received, and the attention button present bit is set to 1. 3. pci_inta# is de-asserted. attention button present bit is cleared to 0. b. power indicator blinks. 4. power indicator control field is set to 10b. 5. power indicator blink message is transmitted downstream. 6. command complete bit is set. 7. pci_inta# is asserted, if enabled. 8. pci_inta# is de-asserted. write to power indicator control field to blink the power led, to indicate board is being powered down. command complete bit is cleared to 0. c. power indicator off. 9. power indicator control field is cleared to 0. 10. after a t pepv delay of 16 ms, command complete bit is set. 11. pci_inta# is asserted, if enabled. 12. pci_inta# is de-asserted. write to the control register power indicator control field, to turn off power to the port. command complete bit is cleared to 0. d. unlock the mrl (manually operated retention latch). 13. mrl sensor present bit is set to 1. 14. mrl sensor change bit is set to 1. 15. pci_inta# is asserted, if enabled. 16. pci_inta# is de-asserted. mrl sensor change bit is cleared to 0. e. remove board from slot. 17. presence detect state bit is cleared to 0. 18. presence detect change bit is set to 1. 19. pci_inta# is asserted, if enabled. 20. pci_inta# is de-asserted. presence detect change bit is cleared to 0.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 205 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 13 power management 13.1 power management capabilities the pex 8114 power management (pm) module inte rfaces with different areas of the pex 8114 to reduce power consumption during idle periods. the pex 8114 supports hardware autonomous power management and software-driven d-state power management. it supports l0s and l1 link states in hardware autonomous active state link pm. it also supports l1, l2/l3 ready, and l3 pci express link states in pci-compatible power management stat es. d0, d3hot, and d3co ld device states and b0 pci bus states are supported in the pci-compat ible power management. because the pex 8114 does not support aux-power, pme generation in the d3cold state is not supported . in forward transparent bridge m ode, the pm module interfaces with the physical layer electrical sub- block, to transition the link state into low-power st ates when it receives a power state change request from an upstream pci express componen t, or when an internal event fo rces the link state entry into low- power states in hardware autonomous pm (active li nk state pm) mode. pci express link states are not directly visible to conventional pci bus driver software, but are derived from the power management state of the components residing on those links. 13.2 pex 8114 power management capabilities summary 13.2.1 general power management capabilities link power management state (l states) ? pci express power management ? l1, l2/l3 ready, and l3 (aux power is not supported ) ? active state power management ? l0s and l1 ? pci bus b0 state device power management state (d states) ? d0 (uninitialized and active) and d3 (hot and cold) support power management event ( pci_pme# ) support in d0 and d3hot power management data register is supported through serial eeprom load 13.2.2 forward bridge-specific power management capabilities pme message generation on the pci express link caused by pci_pme# assertion on the pci bus in forward transparent bridge mode. the pex 8114 has no internal sources that ge nerate pme messages in forward transparent bridge mode. that is , there is no forward transparent bridge mode pci bus hot plug support. therefore, all pme messages re sult from downstream devices asserting pci_pme# input to the pex 8114. only pci d0 and d3 device power states and b0 bus power state are supported in forward transparent bridge mode.
power management plx technology, inc. 206 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 13.2.3 reverse transparent bridge-specific power management capabilities power management events due to hot plug events in reverse transparent bridge mode only (pci hot plug is not supported ). assert pci_pme# on the upstream pci bus: ? upon receiving a pme message from the pci express downstream device, if the pme signaling bit in the power management status and control register is enabled. the pci_pme# signal is de-asserted when the pme status or enable bits are cleared, according to the pci power mgmt. r1.2 . ? caused by a pex 8114 internal hot plug event. generate a pme_turn_off message to the pci e xpress downstream devices when the bridge is requested to be placed into the d3 state. after generating the pme_turn_off message, the pex 8114 waits for the pme_ack message to return prior to entering the d3 state. 13.2.4 device power states the pex 8114 supports the pci express pci-pm d0 , d3hot, and d3cold (no vaux) device power management states. the d1 and d2 states, which are optional in the pci express r1.0a , are not supported . 13.2.4.1 d0 state d0 is divided into two distinct substates, ?uninitia lized? and ?active.? when power is initially applied to the pci express bridge, it enters the d0_uninitialized state. the component remains in the d0_initialized state until the serial eeprom loading and initial link training are complete. a device enters the d0_active state when: single memory access enable occurs combination of the following are set by system software: ? i/o access enable ? memory access enable ? bus master enable 13.2.4.2 d3hot state a device in the d3hot state must be able to respond to co nfiguration accesses, allo wing it to transition by software to the d0_uninitiali zed state. once in d3hot state, the device can be transitioned into d3cold by removing power from the device. in the d3hot state, hot plug operations cause a pme. 13.2.4.3 d3cold state the pex 8114 transitions to the d3cold state when its power is removed. re-applying power causes the device to transition from the d3cold state into the d0_uninitialized state. d3cold state assumes that all previous context is lost; therefore, software must save the necessary context while the device is in the d3hot state.
january, 2007 link power management state expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 207 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 13.2.5 link power management state link power management state is determined by the d-state of its downst ream link. the pex 8114 maintains its pci express link in the l0 state when it operates in standard operational mode (pci pm state in d0_active). active state link po wer management defines a protocol for components in the d0 state to reduce link power, by placing their li nks into a low-power state, and instructs the other end of the link to do likewise. this capability allows hardware autonomous dynamic-link power reduction beyond what is achievable by software-only power management. table 13-1 defines the relationship between the pex 8114 device power state and its downstream link. table 13-1. connected link components power states downstream component d state pex 8114 d state permissible interconnect state power saving actions d0 d0 l0 full power. l0s, l1 (optional) phy transmit lanes are operating in high-impedance state. d1 d0 l1 d2 d3hot d0 or d3hot a a. the pex 8114 initiates a link-state transition of its upstream port to l1 when the port is programmed to d3hot. l1, l2/l3 ready phy transmit lanes are operating in high-impedance state. fc and dll ack/nak timers suspended. pll can be disabled. d3cold (no aux-pwr) d0, d3hot, or d3cold l3 link-off state no power to component.
power management plx technology, inc. 208 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 13.2.6 pex 8114 pci express power management support the pex 8114 supports pci express features that are required or important for pci express bridge power management. table 13-2 defines the supported and non-supported features, and the register bits used for activating feature configuration. reserved bits are not listed. note: power management is not supported in pci-x mode. table 13-2. supported pci express power management capabilities register description supported offset bit(s) y n 40h power management capabilities 7:0 capabilities id default 11h indicates compliance with the pci power mgmt. r1.2 . ? ? ? ? ? ? ? ? ?
january, 2007 pex 8114 pci express power management support expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 209 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 44h power management status and control 1:0 power state reports the pex 8114 power state. 00b = d0 11b = d3hot 01b and 10b = not supported ? ? ? ? ? ? ? ? ? ?
power management plx technology, inc. 210 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 6ch device capabilities 8:6 endpoint l0s acceptable latency not supported. because the pex 8114 is a br idge and not an endpoint, it does not support this feature. 000b = disables the capability ? ? ? ? ? ? ?
january, 2007 pex 8114 pci express power management support expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 211 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 70h device status and control 10 aux power pm enable not supported. cleared to 0. ? ? ? ? ? ?
power management plx technology, inc. 212 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 7ch slot capabilities (reverse transparent bridge mode only) 0 attention button present 0 = attention button is not implemented 1 = attention button is impl emented on the slot chassis of the pex 8114 pci express interface ? ? ? ? ? ? ? ? ?
january, 2007 pex 8114 pci express power management support expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 213 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 80h slot status and control (reverse transparent bridge mode only) 1 power fault detected enable 0 = function disabled 1 = enables a hot plug interrupt or wakeup event on a power fault event on the pex 8114 pci express port ? ? ? ? ? ? ? ?
power management plx technology, inc. 214 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 140h power data note: there are eight registers per port that can be progra mmed through the serial eeprom. each register retains a different power configuration for the por t. each configuration is selected by writing to the data select register data select bits. a 7:0 base power four registers. specifies, in watts, the base power value in the operating condition. this value must be multiplied by the data scale to produce the actual power consumption value. ? ? ? ? ? ? ?
january, 2007 pex 8114 pci express power management support expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 215 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 1e0h power management hot plug user configuration 0 l0s entry idle count time to meet to enter l0s. 0 = idle condition lasts for 1 s 1 = idle condition lasts for 4 s ? ? ? ? ? ?
power management plx technology, inc. 216 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 217 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 14 pex 8114 registers 14.1 introduction this chapter details the pex 8114 registers, and presents the pex 8114 user -programmable registers and the order in which they appear in the register map. register descriptions, when applicable, include details regarding their use and meaning in forward and reverse transparent bridge modes. for further details regarding register names and descriptions, refer to the following specifications: pci r2.3 pci r3.0 pci-to-pci bridge r1.1 pci power mgmt. r1.2 pci express base 1.0a pci express-to-pci/pci-x bridge r1.0 pci-x r1.0b pci-x r2.0a
pex 8114 registers plx technology, inc. 218 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.2 type 1 pex 8114 register map table 14-1. type 1 pex 8114 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h ? type 1 configuration space header registers new capability pointer ( 40h ) 34h ? 3ch next capability pointer ( 48h ) capability id ( 01h ) 40h power management capability registers 44h next capability pointer ( 58h ) capability id ( 05h ) 48h message signaled interr upt capabilit y registers ? 54h next capability pointer ( 68h ) capability id ( 07h ) 58h pci-x capability registers ? 64h next capability pointer ( 00h ) capability id ( 10h ) 68h pci express capabilities registers ? 80h reserved 84h ? f4h plx indirect configuration access mechanism registers f8h fch next capability offset ( fb4h ) 1h extended capability id ( 0003h ) 100h device serial number exte nded capability registers 104h 108h reserved 10ch ? 134h next capability offset ( 148h ) 1h extended capability id ( 0004h ) 138h device power budgeting exte nded capabilit y registers ? 144h next capability offset ( 000h ) 1h extended capability id ( 0002h ) 148h virtual channel extende d capability registers ? 1c4h plx-specific registers 1c8h ? f7ch
january, 2007 type 1 pex 8114 register map expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 219 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pci-x plx-specific registers f80h ? f88h root port registers f8ch ? f9ch pci-x-specific registers fa0h fa4h pci arbiter registers fa8h ? fb0h next capability offset ( 138h ) 1h pci express extended capability id ( 0001h )fb4h advanced error reporti ng capability registers ? ffch table 14-1. type 1 pex 8114 register map (cont.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pex 8114 registers plx technology, inc. 220 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.3 register descriptions the remainder of this chapter details the pex 8114 registers, including: bit/field names register function in forward and reverse transparent bridge modes type whether the power-on/reset value can be modified by way of the pex 8114 serial eeprom initialization feature initial power-on/reset (default) value the register types are grouped by user accessibility. th e types used in this device, and their descriptions, are defined in table 14-2 . table 14-2. register types type description hwinit hardware initialized register or register bit the register bits are initialized by the pex 8114 hardware initia lization mechanism or pex 8114 serial eeprom register initialization feature. the register bits are read-only after initialization and can only be reset with ?power good reset? ( pex_perst# assertion). rc read-clear ? readin g register clears register value the register bits generally indi cate the tally of event occurrences. these registers are used for performance monitoring and, when read, are cleared to 0. ro read-only register or register bit the register bits are read-only and cannot be altered by software. th e register bits can be initialized by the pex 8114 hardware in itialization mechanis m or pex 8114 serial eeprom register initialization feature. r/w read-write register or register bit the register bits are read-write and can be se t or cleared by software to the needed state. r/w1c read-only status ? write 1 to clear status register or register bit the register bits indicate status when read. a status bit set by the sy stem to 1 to indicate status can be cleared by writing 1 to that bit. r/w1cs read-only status ? write 1 to clear status register or register bit the register bits indicate status when read. a status bit set by the sy stem to 1 to indicate status can be cleared by writing 1 to that bit. writing 0 has no effect. bits are not initialized or m odified by reset. devices that consume aux power preserve register values when aux power consumpt ion is enabled (by way of aux power or pme enable). r/ws read-write register or bit the register bits are read-write and can be set or cleared by software to the needed state. bits are not initialized or m odified by reset. devices that consume aux power preserve register values when aux power consumpt ion is enabled (by way of aux power or pme enable).
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 221 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.4 type 1 configuration space header registers table 14-3. type 1 configuration space header register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 device id vendor id 00h status command 04h class code revision id 08h bist (not supported) header type and multi-function primary latency timer cache line size 0ch base address 0 10h base address 1 14h secondary latency timer subordinate bus numb er secondary bus number primary bus number 18h secondary status i/ o limit i/o base 1ch memory limit address m emory base address 20h prefetchable memory limit address prefetchable memory base address 24h prefetchable memory up per base address[63:32] 28h prefetchable memory u pper limit address[63:32] 2ch i/o limit upper 16 bits i/o base upper 16 bits 30h reserved new capability pointer ( 48h if pci-x; 40h if pci express) 34h expansion rom base address (not supported) 38h bridge control interrupt pin interrupt line 3ch
pex 8114 registers plx technology, inc. 222 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-1. 00h product identification bit(s) description type serial eeprom default 15:0 ven do r id unless overwritten by the serial eeprom, returns the plx pci-sig- assigned vendor id. the pex 8114 serial eeprom register initialization capability is used to replace th e plx vendor id with another vendor id. hwinit yes 10b5h 31:16 device id unless overwritten by the serial eeprom, the pex 8114 returns 8114h, the plx-assigned device id. the pe x 8114 serial eeprom register initialization capability is used to replace the plx-assigned device id with another device id. hwinit yes 8114h register 14-2. 04h command/status bit(s) description type serial eeprom default command 0 i/o access enable 0 = pex 8114 ignores i/o access es on the primary interface 1 = pex 8114 responds to i/o accesses on the primary interface r/w yes 0 1 memory access enable 0 = pex 8114 ignores memory acce sses on the primary interface 1 = pex 8114 responds to memory accesses on the primary interface r/w yes 0 2 bus master enable controls the pex 8114 memory and i/o request forwarding in the upstream direction. this bit does not affect th e forwarding of messages nor completions in the upstream or downstream direction. forward transparent bridge mode: 0 = pex 8114 does not respond to memory a nd i/o requests targeting the bridge on the secondary interface 1 = pex 8114 forwards memory and i/o requests reverse transparent bridge mode: 0 = pex 8114 handles memory and i/o requests received on the secondary interface as unsupported requests (u r); for non-posted requests, the pex 8114 returns a completion with ur completion status 1 = pex 8114 forwards memory and i/o requests r/w yes 0 3 special cycle enable not supported. cleared to 0. ro no 0
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 223 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 4 memory write and invalidate used when the pci-x interface is in pci mode. controls bridge ability to convert pci express memory write requests into memory write and invalidate requests on the pci bus. r/w yes 0 5 vga palette snoop valid in reverse transparent bridge mode. pci express-to-pci bridges do not support vga palette snooping. when the bit value is 0, the pex 8114 treats vga palette write accesses as other accesses. when set to 1, vga palette snooping is enabled ( that is , the pex 8114 does not respond to vga palette register writes and snoops the data). refer to section 5.2.1.4, ?vga mode,? for further details. r/w yes 0 6 parity error response enable controls the bridge respon se to data parity errors forwarded from its primary interface ( such as a poisoned tlp or pci bus parity errors). 0 = bridge must ignore data parity errors that it detects a nd continue standard operation (however, records status, such as setting the detected parity error bit) 1 = bridge must set the proper error bits and report the error when a data parity error is detected r/w yes 0 7 idsel stepping/write cycle control not supported. cleared to 0. ro no 0 8 serr# enable controls the signaled system error bit. forward transparent bridge mode: when = 1, enables reporting of fatal an d non-fatal errors detected by the device to the root complex. reverse transparent bridge mode: when = 1, enables reporting of errors de tected by the device by asserting serr# on the pci-x bus. r/w yes 0 9 fast back-to-back transaction enabled not supported. cleared to 0. ro no 0 10 interrupt disable forward transparent bridge mode: 0 = pex 8114 is enabled to gene rate inta# interrupt messages 1 = pex 8114 is prevented from gene rating inta# interrupt messages reverse transparent bridge mode: 0 = pex 8114 is enabled to generate inta# interrupts 1 = pex 8114 is prevented from generating inta# interrupts r/w yes 0 15:11 reserved 00h register 14-2. 04h command/status (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 224 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 status 18:16 reserved 000b 19 interrupt status indicates that an int x # interrupt message is pend ing on behalf of sources internal to the bridge. this bit does not reflect the pci_int x # input status associated with the secondary interface. 0 = no inta# interrupt message is pending 1 = inta# interrupt message is pending internally ro no 0 20 capabilities list required by the pci express base 1.0a as 1 at all times. ro no 1 21 66-mhz capable forward transparent bridge mode: cleared to 0, as required by the pci express base 1.0a . reverse transparent bridge mode: pci-x interface is capable of 66-mhz opera tion; therefore, this bit is set to 1. ro/fwd ro/rev no 0 1 22 reserved 0 23 fast back-to-back transaction capable forward transparent bridge mode: cleared to 0, as required by the pci express base 1.0a . reverse transparent bridge mode: set to 1, indicating fast back-t o-back transaction capability. ro/fwd ro/rev no 0 1 register 14-2. 04h command/status (cont.) bit(s) description type serial eeprom default
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 225 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 24 master data parity error reports data parity error detection by the bridge on the primary interface. set to 1 if the command register parity error response enable bit is set and one of the following conditions occur. forward transparent bridge mode: bridge receives a completion marked poisoned on the primary interface bridge poisons a write reque st on the primary interface reverse transparent bridge mode: bridge, as a bus master on th e primary interface, asserts pci_perr# on a read transaction or detects pci_perr# asserted on a write transaction bridge receives a completion or split completion with a parity error on the secondary interface bridge receives a split completion message for a non-posted write on the primary interface, indicating an un correctable (split) write data error r/w1c yes 0 26:25 devsel timing forward transparent bridge mode: cleared to 00b, as required by the pci express base 1.0a . reverse transparent bridge mode: pertain to pci and pc i-x modes. encode pci_devsel# timing. for the pex 8114, the field is set to 10b, indicating slow speed. ro/fwd ro/rev no no 00b 10b 27 signaled target abort forward transparent bridge mode: when a memory-mapped access payloa d length is greater than 1 dword, the pex 8114 sets this bit to 1. also set to 1 when the bridge completes a request as a transaction target on its primar y interface using completer abort completion status. reverse transparent bridge mode: when the pci-x interface signals target abort, the pex 8114 sets this bit to 1. r/w1c yes 0 register 14-2. 04h command/status (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 226 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 28 received target abort forward transparent bridge mode: set to 1 when the bridge receives a completion with completer abort completion status. reverse transparent bridge mode: set to 1 when the bridge is the transaction master terminated with a target abort or pci-x split completion message indica ting that a target abort was received. r/w1c yes 0 29 received master abort forward transparent bridge mode: set to 1 when the bridge receives a completion with unsupported request completion status. reverse transparent bridge mode: set to 1 when the bridge is the transacti on master terminated by the bridge with master abort status. r/w1c yes 0 30 signaled system error forward transparent bridge mode: set to 1 when the bridge transmits an err_fatal or err_nonfatal message to the root complex. reverse transparent bridge mode: set to 1 when the bridge asserts serr# on the pci-x bus. r/w1c yes 0 31 detected parity error forward transparent bridge mode: set to 1 by the bridge when it receiv es a poisoned tlp or tlp with bad ecrc (read completion or write request) on the primary interface, regardless of the command register parity error response enable bit state. reverse transparent bridge mode: reports detection of an address or data parity error by the bridge on its primary interface. must be set to 1, regardless of the command register parity error response enable bit state, when any of the fo llowing three condi tions is true: detects an address or attribute parity error as a potential target detects a data parity error when the target of a write transaction or pci-x split completion detects a data parity error when the master of a read transaction (immediate read data or pci-x split response) r/w1c yes 0 register 14-2. 04h command/status (cont.) bit(s) description type serial eeprom default
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 227 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-3. 08h class code and revision id bit(s) description type serial eeprom default 7:0 revision id unless overwritten by the serial eeprom, returns bch, the plx-assigned revision id for this version of the pex 8114. the pex 8114 serial eeprom register initialization capability is us ed to replace the plx revision id with another revision id. ro yes bch class code 060400h 15:8 programming interface the pex 8114 supports the pci-to-pci bridge r1.1 requirements, but not subtractive decoding, on its upstream interface. ro yes 00h 23:16 subclass code pci-to-pci bridge. ro yes 04h 31:24 base class code bridge device. ro yes 06h register 14-4. 0ch miscellaneous control bit(s) description type serial eeprom default 7:0 cache line size specifies the system cache line size (in units of dwords). 00h = 1 dword (32-bit bus); 2 dwords (64-bit bus) 01h = 1 dword 02h = 2 dwords 04h = 4 dwords 08h = 8 dwords 10h = 16 dwords 20h = 32 dwords r/w yes 00h 15:8 primary latency timer forward transparent bridge mode: cleared to 00h, as required by the pci express base 1.0a. reverse transparent bridge mode: specifies the master latency timer (i n units of pci bus clocks) when the primary interface is a bus master. ro/fwd r/w/rev r/w/rev no ye s ye s 00h 00h (pci) 40h (pci-x) 22:16 header type the pex 8114 configuration space header adheres to the type 1 pci-to-pci bridge c onfiguration space la yout defined by the pci-to-pci bridge r1.1 . ro no 01h 23 multi-function always 0, because the pex 8114 is a single-function device. ro no 0 31:24 bist not supported. cleared to 00h. ro no 00h
pex 8114 registers plx technology, inc. 228 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-5. 10h base address 0 bit(s) description type serial eeprom default 0 memory space indicator when enabled, the base address regi ster maps the pex 8114 configuration registers into memory space. ro no 0 2:1 memory map type 00b = pex 8114 configuration registers can be mapped anywhere in 32-bit memory address space 10b = pex 8114 configuration registers can be mapped anywhere in 64-bit memory address space 01b, 11b = reserved ro yes 00b 3 prefetchable base address register maps the pe x 8114 configuration registers into non-prefetchable memory space by default. ro no 0 12:4 reserved 000h 31:13 base address base address for plx-spec ific memory-mapped conf iguration space access mechanism. r/w yes 0_0000h register 14-6. 14h base address 1 bit(s) description type serial eeprom default 31:0 base address 1 for 64-bit addressing ( base address 0 register memory map type field = 10b), base address 1 extends base address 0 to provide the upper 32 address bits. r/w yes 0000_0000h
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 229 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-7. 18h bus number bit(s) description type serial eeprom default 7:0 primary bus number record the bus number of the pci bus segment to which the primary interface of this bridge is connect ed. set by configuration software. r/w yes 00h 15:8 secondary bus number record the bus number of the pci bus segment that is the secondary interface of this bridge. se t by configuration software. r/w yes 00h 23:16 subordinate bus number record the bus number of the highest numbered pci bus segment subordinate to this bridge. se t by configuration software. r/w yes 00h 31:24 secondary latency timer forward transparent bridge mode: specifies the master latency timer (i n units of pci bus clocks) when the secondary interface is a bus master. reverse transparent bridge mode: cleared to 00h, as required by the pci express base 1.0a. r/w/fwd r/w/fwd ro/rev ye s ye s no 00h (pci) 40h (pci-x) 00h
pex 8114 registers plx technology, inc. 230 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-8. 1ch secondary status, i/o limit, and i/o base bit(s) description type serial eeprom default i/o base 3:0 i/o base addressing capability 1h = 32-bit address decoding is supported other values are not allowed. ro no 1h 7:4 i/o base address[15:12] the pex 8114 uses the i/o base and i/o limit registers to determine the address range of i/o transactions to forward from the primary interface to the secondary interface or vice versa. i/o base address[15:12] bits spec ify the corresponding pex 8114 i/o base address[15:12]. the pex 8114 assume s i/o base address[11:0] = 000h. the pex 8114 decodes address bits [31:0], and uses the i/o base upper 16 bits and i/o limit upper 16 bits . r/w yes 0h i/o limit 11:8 i/o limit addressing capability 1h = 32-bit address decoding is supported other values are not allowed. ro no 1h 15:12 i/o limit address[15:12] the pex 8114 uses the i/o base and i/o limit registers to determine the address range of i/o transactions to forward from the primary interface to the secondary interface or vice versa. i/o limit address[15:12] specify th e corresponding pex 8114 i/o limit address[15:12]. the pex 8114 assumes addr ess bits [11:0] of the i/o limit address are fffh. the pex 8114 decodes address bits [31:0], and uses the i/o base upper 16 bits and i/o limit upper 16 bits . when the i/o limit address is less th an the i/o base address, the pex 8114 does not forward i/o transactions fro m the primary/upstream bus to its secondary/downstream bus. however, the pex 8114 forwards all i/o transactions from the secondary bus to its primary bus. r/w yes 0h
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 231 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 secondary status 20:16 reserved 0-0h 21 66 mhz enabled forward transparent bridge mode: pci-x interface is capable of 66-mhz operation; therefore, this bit is set to 1. reverse transparent bridge mode: cleared to 0, as required by the pci express base 1.0a . ro/fwd ro/rev no no 1 0 22 reserved 0 23 fast back-to-back transaction enabled forward transparent bridge mode: set to 1, indicating fast back -to-back transactions capable. reverse transparent bridge mode: cleared to 0, as required by the pci express base 1.0a . ro/fwd ro/rev no no 1 0 24 master data parity error reports data parity error detection by th e bridge on the secondary interface. set to 1 if the bridge control register parity error response enable bit is set and one of the following conditions occur. forward transparent bridge mode: bridge, as a bus master on the secondary interface, asserts pci_perr# on a read transaction or detects pci_perr# asserted on a write transaction bridge receives a completion or split completion with a parity error on the secondary interface bridge receives a split completion message for a non-posted write, indicating an uncorrectable (split) write data error reverse transparent bridge mode: bridge receives a completion marked poisoned on the secondary interface bridge poisons a write request on the secondary interface r/w1c yes 0 26:25 devsel timing forward transparent bridge mode: pertain to pci and pci-x modes. encode pci_devsel# timing. for the pex 8114, the field is set to 10b, indicating slow speed. reverse transparent bridge mode: cleared to 00b, as required by the pci express base 1.0a. ro/fwd ro/rev no no 10b 00b 27 signaled target abort forward transparent bridge mode: when the pci-x interface signals target abort, the pex 8114 sets this bit to 1. reverse transparent bridge mode: set to 1 when the bridge completes a request as a transaction target on its secondary interface using comp leter abort completion status. r/w1c yes 0 register 14-8. 1ch secondary status, i/o limit, and i/o base (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 232 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 note: the pex 8114 uses the memory base and limit address registers to determine the address range of non-prefetchable memory transactions to forward from one of its interfaces to the other. 28 received target abort forward transparent bridge mode: set to 1 when the bridge is the transaction master terminated with a target abort or pci-x split completion message i ndicating target abort was received. reverse transparent bridge mode: set to 1 when the bridge receives a completion with completer abort completion status. r/w1c yes 0 29 received master abort forward transparent bridge mode: set to 1 when the bridge is the transaction master terminated by the bridge with master abort status. reverse transparent bridge mode: set to 1 when the bridge receives a completion with unsupported request completion status. r/w1c yes 0 30 received system error forward transparent bridge mode: set to 1 when serr# is asserted on th e secondary interface of the bridge. reverse transparent bridge mode: set to 1 when an err_fatal or err_nonfatal message is received on the secondary interface of the bridge. r/w1c yes 0 31 detected parity error forward transparent bridge mode: reports the detection of an address or data parity error by the bridge on its secondary interface. must be set to 1, regardless of the bridge control register parity error response enable bit state, when any of the following three conditions is true: detects an address or attribute parity error as a potential target detects a data parity error when the target of a write transaction or pci-x split completion detects a data parity error when the master of a read transaction (immediate read data or pci-x split response) reverse transparent bridge mode: set to 1 by the bridge when it receiv es a poisoned tlp or a tlp with bad ecrc (read completion or write request) on the se condary interface, regardless of the bridge control register parity error response enable bit state. r/w1c yes 0 register 14-8. 1ch secondary status, i/o limit, and i/o base (cont.) bit(s) description type serial eeprom default
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 233 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 note: the pex 8114 uses the prefetchable memory base and limit address register to determine the address range of prefetchable memory transactions to forward from one of its interfaces to the other. register 14-9. 20h memory base and limit address bit(s) description type serial eeprom default memory base address 3:0 reserved 0h 15:4 memory base address[31:20] specifies the pex 8114 non-prefetchable memory base address[31:20]. the pex 8114 assumes memory base address[19:0] = 00000h. r/w yes 000h memory limit address 19:16 reserved 0h 31:20 memory limit address[31:20] specifies the pex 8114 non-prefetchab le memory limit address[31:20]. the pex 8114 assumes memory li mit address[19:0] = fffffh. r/w yes 000h register 14-10. 24h prefetchable memory base and limit address bit(s) description type serial eeprom default prefetchable memory base address 3:0 prefetchable memory base capability 1h = pex 8114 defaults to 64-bit pref etchable memory addressing support ro yes 1h 15:4 prefetchable memory base address[31:20] specifies the pex 8114 prefetchable memory base address[31:20]. the pex 8114 assumes prefetchable memory base address[19:0] = 00000h. note: when the prefetchabl e memory limit addr ess is less than the prefetchable memory base address, the pex 8114 does not forward prefetchable memory transactions from the upstream bus to its downstream bus. however, the pex 8114 forwards all memory transactions from the downstream bus to its upstream bus. r/w yes 000h prefetchable memory limit address 19:16 prefetchable memory limit capability 1h = pex 8114 defaults to 64-bit pref etchable memory addressing support ro yes 1h 31:20 prefetchable memory limit address[31:20] specifies the pex 8114 prefetchable memory base address[31:20]. the pex 8114 assumes prefetchable memory base address[19:0] = fffffh. r/w yes 000h
pex 8114 registers plx technology, inc. 234 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-11. 28h prefetchable memory upper base address[63:32] bit(s) description type serial eeprom default 31:0 prefetchable memory base address[63:32] the pex 8114 uses this register for prefetchable memory upper base address[63:32]. r/w yes 0000_0000h register 14-12. 2ch prefetchable memory upper limit address[63:32] bit(s) description type serial eeprom default 31:0 prefetchable memory limit address[63:32] the pex 8114 uses this register fo r prefetchable memory upper limit address[63:32]. r/w yes 0000_0000h register 14-13. 30h i/o base address[31:16] and i/o limit address[31:16] bit(s) description type serial eeprom default 15:0 i/o base upper 16 bits the pex 8114 uses this register for i/o base address[31:16]. r/w yes 0000h 31:16 i/o limit upper 16 bits the pex 8114 uses this register for i/o limit address[31:16]. r/w yes 0000h
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 235 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-14. 34h new capability pointer bit(s) description type serial eeprom default 7:0 new capability pointer pci-x interface: default 48h points to the message signaled inte rrupt capability list register. pci express interface: default 40h points to the power management capability list register. ro no 48h (pci-x) 40h (pci express) 31:8 reserved 0000_00h register 14-15. 38h expansion rom base address bit(s) description type serial eeprom default 31:0 expansion rom base address not supported. cleared to 0000_0000h. ro no 0000_0000h
pex 8114 registers plx technology, inc. 236 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-16. 3ch bridge control and interrupt signal bit(s) description type serial eeprom default 7:0 interrupt line the pex 8114 does not use this register, but provides it for operating system and device driver use. r/w yes 00h 15:8 interrupt pin identifies the conventional pci interr upt message that the pex 8114 uses. 01h maps to conventional pci inta# interrupt message. ro no 01h bridge control 16 parity error response enable controls bridge response to address a nd data parity errors on the secondary interface. if this bit is set, the bridge must detect and re port parity errors on the secondary interface. if cleared, th e bridge must ignore parity errors that it detects on the secondary inte rface and continue standard operation. a bridge must generate pa rity, although parity erro r reporting is disabled. r/w yes 0 17 serr# enable forward transparent bridge mode: controls forwarding of secondary interf ace serr# assertions to the primary interface. the bridge transmits an err_fatal or err_nonfatal cycle on the primary interface when all of the following conditions are true: serr# is asserted on the secondary interface this bit is set command register serr# enable bit is set reverse transparent bridge mode: controls forwarding of err_fatal and err_nonfatal from the secondary interface to the primary interface by asserting serr# when all the following conditions are true. err_fatal or err_nonfatal is received on the secondary interface this bit is set command register serr# enable bit is set when set to 1, and the command register serr# enable bit value is 1, enables the signaled system error bit. r/w yes 0 18 isa enable refer to section 5.2.1.3, ?isa mode,? for details. r/w yes 0 19 vga enable refer to section 5.2.1.4, ?vga mode,? and the pci r3.0 for details. r/w yes 0
january, 2007 type 1 configuration space header registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 237 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 20 vga 16-bit decode refer to section 5.2.1.4, ?vga mode,? and the pci r3.0 for details. r/w yes 0 21 master abort mode controls bridge behavior after it re ceives a master abort termination ( such as , an unsupported request on pci e xpress) on either interface. this bit does not affect the behavior of the bridge when forwarding a ur completion from pci express to the pci-x interface, if the pci-x interface is operating in pci-x mode. 0 = do not report master aborts. return ffff_ffffh on reads and discard data on writes initiated from the pci-x interface (pci-to-pci express). for posted transactions initiated from the pci express interface (pci express- to-pci), no action is taken ( that is , all data is discarded). 1 = report ur completions from pci express by signaling target abort on the pci-x interface operating in conventional pci mode (pci-to-pci express). for posted transactions initiated from the pci express interface (pci express-to-pc i) that experience a master abort on the pci-x interface, the bridge must return err_fatal or err_nonfatal on the primary interface (provided the command register serr# enable bit is set). r/w yes 0 22 secondary bus reset forward transparent bridge mode: setting this bit causes rst# to assert on the secondary interface. reverse transparent bridge mode: setting this bit causes a hot re set to communicate on the pex 8114 secondary interface. r/w yes 0 23 fast back-to-back transaction enable not supported. cleared to 0. ro no 0 register 14-16. 3ch bridge control and interrupt signal (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 238 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 24 primary discard timer pertains to the pci bus in conventional pci mode and reverse transparent bridge mode. selects the number of pci clocks that the bridge waits for a master on the primary interface to repeat a dela yed transaction request. the counter starts after the delayed completion (the delayed transaction completion on the secondary interface) reaches the head of the bridge?s upstream queue ( that is , all ordering requirement s are satisfied and the bridge is ready to complete the delayed transaction with the originating master on the primary bus). if the originating master does not repeat the transaction before the counter expires, the bridge deletes the delayed transaction from its queue and sets the discard timer status bit. 0 = primary discard timer counts 2 15 pci clock cycles 1 = primary discard timer counts 2 10 pci clock cycles ro/fwd r/w/rev no ye s 0 0 25 secondary discard timer pertains to the pci bus in conventional pci mode and forward transparent bridge mode. selects the number of pci clocks th e bridge waits for a master on the secondary interface to repeat a dela yed transaction request. the counter starts after the completion (pci express completion associated with the delayed transaction request ) reaches the head of the bridge?s downstream queue ( that is , all ordering requirements are sa tisfied and the bridge is ready to complete the delayed transaction with the originating master on the secondary bus). if the originating mast er does not repeat the transaction before the counter expires, the bridge deletes the delaye d transaction from its queue and set the discard timer status bit. 0 = secondary discard timer counts 2 15 pci clock cycles 1 = secondary discard timer counts 2 10 pci clock cycles r/w/fwd ro/rev ye s no 0 0 26 discard timer status pertains to the pci bus in conventional pci mode. set to 1 when the primary discard timer or secondary discard timer expires and a delayed completion is di scarded from a queue in the bridge. the default state of this bit after reset must be 0. once set, remains set until it is reset by writing 1 to this bit location. r/w1c yes 0 27 discard timer serr# enable pertains to the pci bus in conventional pci mode. when set to 1, enables the bridge to generate an err_fatal or err_nonfatal transaction when the secondary discard timer expires and a delayed transaction is disc arded from a queue in the bridge. r/w yes 0 31:28 reserved 0h register 14-16. 3ch bridge control and interrupt signal (cont.) bit(s) description type serial eeprom default
january, 2007 power manage ment capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 239 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.5 power management capability registers this section details the pex 8114 power management registers. table 14-4 defines the register map. table 14-4. power management capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 power management capabilit ies next capability pointer ( 48h ) capability id ( 01h ) 40h data power management control/ status bridge extensions power management st atus and control 44h register 14-17. 40h power management capability list, capabilities bit(s) description type serial eeprom default power management capability list 7:0 capability id default 01h indicates that the data structur e currently pointed to is the pci power management data structure. ro yes 01h 15:8 next capability pointer default 48h points to the message signaled inte rrupt capability list register. ro yes 48h power management capabilities 18:16 ve rsi o n default 011b indicates compliance with the pci power mgmt. r1.2 . ro yes 011b 19 pme clock set to 1, as required by the pci express base 1.0a. ro no 1 20 reserved 0h 21 device-specific initialization default 0 indicates that devi ce-specific initialization is not required. ro yes 0 24:22 aux current not supported. default 000b indicates that the pex 8114 does not support auxiliary current requirements. ro yes 000b 25 d1 support not supported. default 0 indicates that the pex 8114 does not support the d1 power state. ro no 0 26 d2 support not supported. default 0 indicates that the pex 8114 does not support the d2 power state. ro no 0 31:27 pme support default 11001b indicates that the pex 8114 forwards pme messages in the d0, d3hot, and d3cold power states. ro yes 11001b
pex 8114 registers plx technology, inc. 240 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-18. 44h power management status and control bit(s) description type serial eeprom default power management status and control 1:0 power state reports the pex 8114 power state. 00b = d0 11b = d3hot 01b and 10b = not supported r/w yes 00b 2 reserved 0 3 no soft reset when set to 1, indicates that devices transitioning from d3hot to d0 because of power state commands do not perform an internal reset. ro yes 1 7:4 reserved 0h 8 pme enable 0 = disables pme generation by the pex 8114 a 1 = enables pme generation by the pex 8114 a. because the pex 8114 does not support auxiliary power, this bit is not sticky, and is cleared to 0 at power-on reset. r/ws no 0 12:9 data select r/w by serial eeprom mode b . bits [12:9] select the data and data scale registers. 0h = d0 power consumed 3h = d3hot power consumed 4h = d0 power dissipated 7h = d3hot power dissipated b. without serial eeprom, reads return 00h for data scale and data registers (for all data selects). ro yes 0h not supported. ro for hardware au to-configuration. ro no 0h 14:13 data scale r/w by serial eeprom mode b . there are four internal data scale registers. bits [12:9], data select , select the data scale register. ro yes 00b 15 pme status 0 = pme is not generated by the pex 8114 a 1 = pme is generated by the pex 8114 r/w1c no 0 power management control/status bridge extensions 21:16 reserved 0-0h 22 b2/b3 support cleared to 0, as required by the pci power mgmt. r1.2 . ro no 0 23 bus power/clock control enable cleared to 0, as required by the pci power mgmt. r1.2 . ro no 0 power management data 31:24 data r/w by serial eeprom mode b . there are four internal data registers. bits [12:9], data select , select the data register. ro yes 00h
january, 2007 message signaled interrupt capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 241 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.6 message signaled interrupt capability registers this section details the pex 8114 message signaled interrupt (msi) capability registers. table 14-5 defines the register map. table 14-5. message signaled interrupt capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 message signaled interrupt control next capability pointer ( 58h if pci-x; 68h if pci express) capability id ( 05h ) 48h lower message address[31:0] 4ch upper message address[63:32] 50h reserved message data 54h register 14-19. 48h message signaled interrupt capability list, control bit(s) description type serial eeprom default message signaled inte rrupt capability list 7:0 capability id set to 05h , as required by the pci r3.0. ro yes 05h 15:8 next capability pointer pci-x interface: set to 58h to point to the pex 8114 pci-x capability registers. pci express interface: set to 68h to point to the pex 8114 pci express capabilities registers. ro yes 58h (pci-x) 68h (pci express) message signaled interrupt control 16 msi enable 0 = message signaled interrupts for the pex 8114 are disabled 1 = message signaled interrupts for the pex 8114 are enabled r/w yes 0 19:17 multiple message capable 000b = pex 8114 is requesting one message ? only value supported ro yes 000b 22:20 multiple message enable 000b = pex 8114 contains one allocated message ? only value supported r/w yes 000b 23 msi 64-bit address capable 1 = pex 8114 is capable of gene rating 64-bit message signaled interrupt addresses ro yes 1 31:24 reserved 00h
pex 8114 registers plx technology, inc. 242 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-20. 4ch lower message address[31:0] bit(s) description type serial eeprom default 1:0 reserved 00b 31:2 message address[31:2] msi write transaction lower address[31:2]. note: refer to offset 50h for upper message address[63:32]. r/w yes 0000_0000h register 14-21. 50h upper message address[63:32] bit(s) description type serial eeprom default 31:0 message address[63:32] msi write transaction upper address[63:32]. note: refer to offset 4ch for lower message address[31:2]. r/w yes 0000_0000h register 14-22. 54h message data bit(s) description type serial eeprom default 15:0 message data msi write transaction payload. r/w yes 0000h 31:16 reserved 0000h
january, 2007 pci-x capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 243 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.7 pci-x capability registers this section details the pex 8114 pci-x capability registers. table 14-6 defines the register map. table 14-6. pci-x capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci-x secondary status ne xt capability pointer ( 68h ) capability id ( 07h ) 58h pci-x bridge status 5ch upstream split transaction control 60h downstream split transaction control 64h register 14-23. 58h pci-x capability list, secondary status bit(s) description type serial eeprom default pci-x capability list 7:0 capability id set to 07h . ro no 07h 15:8 next capability pointer set to 68h to point to pex 8114 pci expr ess capabilities registers. ro no 68h pci-x secondary status 16 64-bit device pertains to the pci-x interface in forward transparent bridge mode. when set to 1, indicates that the pci-x interface has 64 ad lines. ro/fwd ro/rev ye s no 1 0 17 133 mhz capable pertains to the pci-x interface in reverse transparent bridge mode and pci-x mode. when set to 1, indicates that th e pci-x interface is capable of operating with a clock frequency of 133 mhz. 0 = maximum operating clock frequency is 66 mhz 1 = maximum operating clock frequency is 133 mhz ro/fwd ro/rev no no 1 0 18 split completion discarded pertains to the pci-x interface in forward transparent bridge mode.this bit is set if the bridge discards a split co mpletion propagating downstream toward the secondary bus because the re quester does not accept it. 0 = split completion is not discarded 1 = split completion is not discarded r/w1c/fwd ro/rev no no 0 0 19 unexpected split completion pertains to the pci-x interface in forward transparent bridge mode and the pci express interface in reverse transparent bridge mode. this bit is set if a split completion is received on the pci-x interface and there is no matching request. 0 = unexpected split co mpletion is not received 1 = unexpected split completion is received r/w1c no 0
pex 8114 registers plx technology, inc. 244 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 20 split completi on overrun pertains to the pci-x interface in forward transparent bridge mode. this bit is set if the bridge terminates a spl it completion on the secondary bus with retry or disconnect at next adb beca use the bridge buffers are full. used by algorithms that optimize the downstream split transaction commitment limit field setting. (refer to the pci-x r2.0a , appendix d, for further details.) the bridge is also permitted to set this bit in other situations that indicate that the bridge commitment limit is overly high. for example , if the bridge stores immediate completion data in the same buffer area as split completion data, the completer executes the transaction as an immediate transaction, and the bri dge disconnects the transact ion because the buffers are full. 0 = bridge accepted all split completions 1 = bridge terminated a split comple tion with retry or disconnect at next adb because the bridge buffers are full r/w1c/fwd ro/rev no no 0 0 21 split request delayed pertains to the pci-x interface in forward transparent bridge mode and the pci express interface in reverse transparent bridge mode. this bit is set when the pci-x interface cannot forward a transaction due to a lack of space specified in the downstream split transaction control register split transaction commitment limit field. (refer to the pci-x r2.0a , appendix d, for further details.) 0 = bridge does not delayed a split request 1 = bridge does delay a split request r/w1c/fwd r/w1c/rev no no 0 0 25:22 secondary clock bus mode and frequency pertains to the pci-x interface in forward transparent bridge mode. provides a code that indicates to software th e mode and frequency in which the pci-x interface is operating. error max. clock min. clock reg mode protection freq. (mhz) period (ns) 0h conventional pci parity n/a n/a 1h pci-x mode 1 parity 66 15 2h pci-x mode 1 parity 100 10 3h pci-x mode 1 parity 133 7.5 ro/fwd ro/rev no no 0h 0h 27:26 reserved 00b 29:28 pci-x capabilities list item version pertains to the pci-x interface in forward transparent bridge mode. indicates the pci-x capabilities list item format, and whether the bridge supports ecc in mode 1. value version ecc support capabilities list item size 00b 0 none 16 bytes 01b 1 mode 2, not mode 1 32 bytes 10b 2 mode 1 or modes 1 and 2 32 bytes 11b reserved ro/fwd ro/rev no no 00b 00b 30 pci-x 266 capable not supported. cleared to 0. ro no 0 31 pci-x 533 capable not supported. cleared to 0. ro no 0 register 14-23. 58h pci-x capability list, secondary status (cont.) bit(s) description type serial eeprom default
january, 2007 pci-x capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 245 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-24. 5ch pci-x bridge status bit(s) description type serial eeprom default 2:0 function number contains the pex 8114 function number. this number is used in the completer id. ro no 000b 7:3 device number contains the pex 8114 device number. forward transparent bridge mode: this number is assigned by the number in the device number field of the type 0 configuration write request target ed to this device on the pci express interface. reverse transparent bridge mode: the device number is assigned by th e device number field in the type 0 configuration transaction targeted to the device on the pci-x interface. this number is used in the completer id. ro/fwd ro/rev no no 00h 1fh 15:8 bus number this number is a second regi ster for software to read the value of the bus number written into the primary bus number at offset 18h . this number is used in the completer id. ro no 00h 16 64-bit device pertains to the pci-x interface in reve rse transparent bridge mode. when set to 1, indicates that the pc i-x interface has 64 ad lines. ro/fwd ro/rev no yes 0 1 17 133 mhz capable pertains to the pci-x interface in forward transparent bridge mode and pci-x mode. when set to 1, indicates that the pci-x interface is capable of operating with a clock frequency of 133 mhz. 0 = maximum operating cloc k frequency is 66 mhz 1 = maximum operating cloc k frequency is 133 mhz ro/fwd ro/rev no no 0 1 18 split completion discarded pertains to the pci-x interface in revers e transparent bridge mode. this bit is set if the bridge discards a split co mpletion propagating downstream toward the secondary bus because the re quester would not accept it. 0 = split completion is not discarded 1 = split completion is discarded ro/fwd r/w1c/rev no no 0 0 19 unexpected split completion pertains to the pci-x interface in reverse transparent bridge mode and the pci express interface in forward transpar ent bridge mode. this bit is set if a split completion is received on the pci-x interface and there is no matching request. 0 = unexpected split completion is not received 1 = unexpected split completion was received r/w1c/fwd r/w1c/rev no no 0 0
pex 8114 registers plx technology, inc. 246 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 20 split completion overrun pertains to the pci-x interface in reverse transparent bridge mode. this bit is set if the bridge terminates a split co mpletion on the secondary bus with retry or disconnect at next adb becaus e the bridge buffers are full. used by algorithms that optimize the downstream split transaction commitment limit field setting. (refer to the pci-x r2.0a , appendix d, for further details.) the bridge is also permitted to set th is bit in other situations that indicate that the bridge commitment limit is overly high. for example , if the bridge stores immediate completion data in the same buffer area as split completion data, the completer executes the transaction as an immediate transaction, and the bridge disconnect s the transaction because the buffers became full. 0 = bridge accepted all split completions 1 = bridge terminated a split completi on with retry or disconnect at next adb because the bridge buffers are full ro/fwd r/w1c/rev no no 0 0 21 split request delayed pertains to the pci-x interface in reverse transparent bridge mode and the pci express interface in forward transparent bridge mode. this bit is set when the pci-x interface cannot forward a transaction due to a lack of space specified in the downstream split transaction control register split transaction commitment limit field. (refer to the pci-x r2.0a , appendix d, for further details.) 0 = bridge is not de layed a split request 1 = bridge delayed a split request r/w1c/fwd r/w1c/rev no no 0 0 28:22 reserved 00h 29 device id messaging capable not supported. cleared to 0. ro no 0 30 pci-x 266 capable not supported. cleared to 0. ro no 0 31 pci-x 533 capable not supported. cleared to 0. ro no 0 register 14-24. 5ch pci-x bridge status (cont.) bit(s) description type serial eeprom default
january, 2007 pci-x capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 247 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-25. 60h upstream split transaction control bit(s) description type serial eeprom default 15:0 split transaction capacity indicates the buffer size (in adqs) available for storage of completions for requests on the secondary interface that are addressing completers on the primary interface. ro no 0010h 31:16 split transaction commitment limit indicates the sequence size (in units of adqs) for read transactions forwarded by the bridge from reques ters on the secondary interface, to completers on the primary interface. (refer to the pci-x r2.0a , appendix d, for a detailed discussion of split transac tion commitment.) when the bridge stores split read completions in the same buffer as other split completions, this register indicates the size of all upstream split transactions of these types that the bridge is permitted to commit to at one time. software is permitted to program this register to a value greater than or equal to the contents of the split transaction capacity register. a value less than the contents of the split transaction capac ity register causes unspecified results. when this register is set to ffffh, the br idge is permitted to forward all split requests of any size, regardless of av ailable buffer space (an exception is described in section 2.6, ?strapping signals? ). software is permitted to change this register at any time. the most recent value of the register is used each time the bridge forwards a split transaction. if the register value is set to ffffh, the bridge does not track the outstanding com mitment. if the register is later set to another value, the bridge does not accu rately track outstanding commitments until all outstanding co mmitments complete. systems that require accurate limitation of split transactions must never set this register to ffffh. they must quiesce all devices that initiate traffic that crosses the bridge in this direction af ter the register setting is changed from ffffh. an algorithm for setting this regi ster is not specified. system software is permitted to use any method for selecting the value for this register. individual devices and device drivers ar e not permitted to change the value of this register except under control of a sy stem-level configuration routine. (refer to the pci-x r2.0a , appendix d, for details a nd setting recommendations.) default value of this field equals the value stored in the split transaction capacity field. r/w yes 0010h
pex 8114 registers plx technology, inc. 248 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-26. 64h downstream split transaction control bit(s) description type serial eeprom default 15:0 split transaction capacity indicates the buffer size (in adqs) available for storage of completions for requests on the primary interface th at are addressing completers on the secondary interface. ro no 0010h 31:16 split transaction commitment limit indicates the sequence si ze (in units of adqs) for read transactions forwarded by the bridge from reque sters on the primary interface, to completers on the secondary interface. (refer to the pci-x r2.0a , appendix d, for a detailed discussion of split transact ion commitment.) if the bridge stores split read completions in the same buffer as other split completions, this register indicates the size of all downstream split tr ansactions of these types that the bridge is permitted to commit to at one time. software is permitted to pr ogram this register to a value greater than or equal to the contents of the split transaction capacity register. a value less than the contents of the split transa ction capacity register ca uses unspecifi ed results. if this register is set to ffffh, the bridge is permitted to forward all split request of any size, regardle ss of available buffer space. software is permitted to change this register at any time. the mo st recent value of the register is used each time the bridge forw ards a split transaction. when the register value is set to ffffh, the bridge does not track the outstanding comm itment. if the register is later se t to another value, the bridge does not accurately track outstandi ng commitments until all outstanding commitments complete. systems that require accurate limitation of split transactions must never set this register to ffffh. they must quiesce all devices that in itiate traffic that crosses the bridge in this direction af ter the register setting is changed from ffffh. an algorithm for setting this register is not specified. system software is permitted to use any method for selecting the value for this register. individual devices and device drivers ar e not permitted to change the value of this register except under control of a system-level conf iguration routine. (refer to the pci-x r2.0a for details and setting recommendations.) default value of this field equals the value stored in the split transaction capacity field. r/w yes 0010h
january, 2007 pci expre ss capabilities registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 249 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.8 pci express capabilities registers this section details the pex 8114 pci express capabilities registers. hot plug capability, command, status, and events are included in these registers. table 14-7 defines the register map. table 14-7. pci express capabilities register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci express capabilities next capability pointer ( 00h ) capability id ( 10h ) 68h device capabilities 6ch device status device control 70h link capabilities 74h link status reserved link control 78h slot capabilities (reverse tr ansparent bridge mode only) 7ch slot status (reverse transparent bridge mode only) s lot control (reverse transparent bridge mode only) 80h register 14-27. 68h pci express capability list, capabilities bit(s) description type serial eeprom default pci express capability list 7:0 capability id set to 10h, as required by the pci express base 1.0a. ro yes 10h 15:8 next capability pointer 00h = pci express capabilities is the last capability in the pex 8114 capabilities list the pex 8114 extended capab ilities list starts at 100h . ro yes 00h pci express capabilities 19:16 capability version the pex 8114 sets this field to 1h, as required by the pci express base 1.0a. ro yes 1h 23:20 device/port type set at reset, as required by the pci express base 1.0a. ro/fwd ro/rev yes yes 7h 8h 24 slot implemented forward transparent bridge mode: 0 = disables or connects to an upstream port reverse transparent bridge mode: 0 = disables or connects to an integrated component a 1 = indicates that the downstream port c onnects to a slot, as opposed to connected to an integrated component or disabled a. the pex 8114 serial eeprom register initialization capability is used to change this value to 0h, indicating that the pex 8114 downstream port connects to an integrated component or is disabled. ro/fwd ro/rev no yes 0 1 29:25 interrupt me ssage number the serial eeprom writes 0000_0b, because the base message and msi messages are the same. ro yes 0000_0b 31:30 reserved 00b
pex 8114 registers plx technology, inc. 250 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-28. 6ch device capabilities bit(s) description type serial eeprom default 2:0 maximum payload size supported 000b = pex 8114 supports 128-byte maximum payload 001b = pex 8114 supports 256-byte maximum payload no other values are supported. ro yes 001b 4:3 phantom functions not supported. cleared to 00b. ro yes 00b 5 extended tag field 0 = maximum tag field is 5 bits 1 = maximum tag field is 8 bits ro yes 0 8:6 endpoint l0s acceptable latency not supported. because the pex 8114 is a br idge and not an endpoint, it does not support this feature. 000b = disables the capability ro yes 000b 11:9 endpoint l1 acceptable latency not supported. because the pex 8114 is a br idge and not an endpoint, it does not support this feature. 000b = disables the capability ro yes 000b
january, 2007 pci expre ss capabilities registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 251 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 12 attention button present forward transparent bridge mode: for the pex 8114 pci express interface, value of 1 indicates that an attention button is implemented on that adapter board. the pex 8114 serial eeprom register initialization capability is used to change this value to 0, indicat ing that an attention button is not present on an adapter board for which the pex 8114 provides the system interface. reverse transparent bridge mode: not valid for reverse transparent bridge mode. hwinit/fwd ro/rev yes no 1 0 13 attention indicator present forward transparent bridge mode: for the pex 8114 pci express interface, value of 1 indicates that an attention indicator is implemented on the adapter board. the pex 8114 serial eeprom register initialization capability is used to change this value to 0, indicati ng that an attent ion indicator is not present on an adapter board for which the pex 8114 provides the system interface. reverse transparent bridge mode: not valid for reverse transparent bridge mode. hwinit/fwd ro/rev yes no 1 0 14 power indicator present forward transparent bridge mode: for the pex 8114 pci express interface, value of 1 indica tes that a power indicator is implemented on the adapter board. the pex 8114 serial eeprom register initialization capability is used to change this value to 0, indicat ing that a power indicator is not present on an adapter board for which the pex 8114 provides the system interface. reverse transparent bridge mode: not valid for reverse transparent bridge mode. hwinit/fwd ro/rev yes no 1 0 17:15 reserved 000b 25:18 captured slot power limit value forward transparent bridge mode: the upper limit on power supplied by the slot to the pex 8114 is determined by multiplying the value in this field by the value in the captured slot power limit scale field. reverse transparent bridge mode: not valid for reverse transparent bridge mode. ro/fwd ro/rev yes no 00h 00h 27:26 captured slot power limit scale forward transparent bridge mode: the upper limit on power supplied by the slot to the pex 8114 is determined by multiplying the value in this field by the value in the captured slot power limit value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 reverse transparent bridge mode: not valid for reverse transparent bridge mode. ro/fwd ro/rev yes no 00b 00b 31:28 reserved 0h register 14-28. 6ch device capabilities (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 252 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-29. 70h device status and control bit(s) description type serial eeprom default device control 0 correctable error reporting enabled 0 = disables 1 = enables pex 8114 to report correctable errors r/w yes 0 1 non-fatal error reporting enabled 0 = disables 1 = enables pex 8114 to report non-fatal errors r/w yes 0 2 fatal error reporting enabled 0 = disables 1 = enables pex 8114 to report fatal errors r/w yes 0 3 unsupported request reporting enable 0 = disables 1 = enables pex 8114 to report unsupported request errors r/w yes 0 4 relaxed ordering enabled not supported. cleared to 0. ro no 0 7:5 maximum payload size power-on/reset value is 000b, indicating that in itially the pex 8114 is configured to support a maximum payload size of 128 by tes. software can change this field to configure the pex 8114 to support payload sizes of 256 or 128. software must not change this field to values other than those indicated by the device capabilities register maximum payload size supported field. r/w yes 000b 8 extended tag field enabled not supported. cleared to 0. ro no 0 9 phantom functions enable not supported. cleared to 0. ro no 0 10 aux power pm enable not supported. cleared to 0. ro no 0 11 no snoop enable not supported. cleared to 0. ro no 0 14:12 maximum read request size specifies the maximum size (in bytes) of a read request generated by the pex 8114. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes (default) 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = reserved r/w yes 010b 15 bridge configuration retry enable r/w yes 0
january, 2007 pci expre ss capabilities registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 253 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 device status 16 correctable error detected 1 = pex 8114 detected a correctable error set when the pex 8114 detects a correct able error, regardless of the correctable error reporting enabled bit state. r/w1c yes 0 17 non-fatal error detected 1 = pex 8114 detected a non-fatal error set when the pex 8114 detects a non- fatal error, regardless of the non-fatal error reporting enabled bit state. r/w1c yes 0 18 fatal error detected 1 = pex 8114 detected a fatal error set when the pex 8114 detects a fatal error, regardless of the fatal error reporting enabled bit state. r/w1c yes 0 19 unsupported request detected 1 = pex 8114 detected an unsupported request set when the pex 8114 detects an un supported request, regardless of the unsupported request reporting enable bit state. r/w1c yes 0 20 aux power detected not supported. cleared to 0. ro no 0 21 transactions pending when set to 1, indicates that the br idge is waiting for a completion from an outstanding transaction. ro no 0 31:22 reserved 000h register 14-30. 74h link capabilities bit(s) description type serial eeprom default 3:0 maximum link speed set to 0001b, as required by the pci express base 1.0a for 2.5 gbps pci express link. ro yes 0001b 9:4 maximum link width maximum link width is x4 = 00_0100b. ro no 00_0100b 11:10 active-state power management support 01b = pex 8114 supports the l0s link power state 11b = pex 8114 supports the l0s and l1 link power states all other values are reserved . ro yes 11b 14:12 l0s exit latency 101b = pex 8114 l0s exit latency is between 1 and 2 s ro no 101b 17:15 l1 exit latency 101b = pex 8114 l1 exit latency is between 16 and 32 s ro yes 101b 23:18 reserved 0-0h 31:24 port number port number is 0. ro no 00h register 14-29. 70h device status and control (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 254 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-31. 78h link status and control bit(s) description type serial eeprom default link control 1:0 active-state power management control 00b = disables l0s and l1 entries for the pex 8114 pci express port a 01b = enables only l0s entry 10b = enables only l1 entry 11b = enables both l0s and l1 entries r/w yes 00b 2 reserved 0 3 read completion boundary specifies the naturally occurring bounda ry on which a read request can be broken up into smaller completions than the original size of the request. defined encodings are: 0 = 64 bytes 1 = 128 bytes r/w yes 0 4 link disable forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: when set to 1, disables the pe x 8114 downstream pci express link. ro/fwd r/w/rev no yes 0 0 5 retrain link forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: writing 1 to this bit causes the pex 8114 to initiate retraining of its pci express link. when read, always returns 0. ro/fwd ro/rev no yes 0 0 6 common clock configuration 0 = pex 8114 and the device at the other end of the pci express link are operating with an asynchronous reference clock 1 = pex 8114 and the device at the other end of the pci express link are operating with a distributed common reference clock r/w yes 0 7 extended sync when set to 1, causes the pex 8114 to transmit: 4,096 fts ordered-sets in the l0s state followed by a single skip ordered-set prior to entering the l0 state finally, transmission of 1,024 ts1 orde red-sets in the recovery state r/w yes 0 15:8 reserved 00h
january, 2007 pci expre ss capabilities registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 255 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 link status 19:16 link speed set to 1h, as required by the pci express base 1.0a for 2.5 gbps pci express link. ro yes 1h 25:20 negotiated link width link width is determined by negotia ted value with attached port/lane. 00_0001b = x1 00_0010b = x2 00_0100b = x4 (default) all other values are not supported . ro yes 00_0100b 26 training error forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: when set to 1, indicates that the pex 8114 detected a link training error. ro/fwd ro/rev no yes 0 0 27 link training forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: when set to 1, indicates that the pe x 8114 pci express interface requested link training and the link training is in progress or about to start. ro/fwd ro/rev no no 0 0 28 slot clock configuration 0 = indicates pex 8114 uses an independent clock 1 = indicates pex 8114 uses the same physic al reference clock that the platform provides on the connector hwinit yes 0 31:29 reserved 000b a. the port receiver must be capable of entering the l0 s state, regardless of whether the state is disabled. register 14-31. 78h link status and control (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 256 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-32. 7ch slot capabilities (reverse transparent bridge mode only) bit(s) description type serial eeprom default 0 attention button present forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = attention button is not implemented 1 = attention button is implemented on the slot chassis of the pex 8114 pci express interface ro/fwd hwinit/rev no yes 0 1 1 power controller present forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = power controller is not implemented 1 = power controller is implemented for the slot of the pex 8114 pci express interface ro/fwd hwinit/rev no yes 0 1 2 mrl sensor present forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = mrl sensor is not implemented 1 = mrl sensor is implemented on the slot chassis of the pex 8114 pci express interface ro/fwd hwinit/rev no yes 0 1 3 attention indicator present forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = attention indicato r is not implemented 1 = attention indicator is implemented on the slot chassis of the pex 8114 pci express interface ro/fwd hwinit/rev no yes 0 1
january, 2007 pci expre ss capabilities registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 257 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 4 power indicator present forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = power indicator is not implemented 1 = power indicator is implemented on the slot chassis of the pex 8114 pci express interface ro/fwd hwinit/rev no yes 0 1 5 hot plug surprise forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = no device in the pex 8114 pci e xpress interface slot is removed from the system, without prior notification 1 = device in the pex 8114 pci express interface slot can be removed from the system, without prior notification ro/fwd hwinit/rev no yes 0 0 6 hot plug capable forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = pex 8114 pci express interface slot is not capable of supporting hot plug operations 1 = pex 8114 pci express interface slot is capable of supporting hot plug operations ro/fwd hwinit/rev no yes 0 1 14:7 slot power limit value forward transparent bridge mode: do not change in forward transparent bridge mode. reverse transparent bridge mode: the maximum power available from the pex 8114 pci express interface is determined by multiplying the value in this field (expressed in decimal; 25d = 19h) by the value specified by the slot power limit scale field. ro/fwd hwinit/rev no yes 00h 19h 16:15 slot power limit scale forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: the maximum power available from the pex 8114 pci express interface is determined by multiplying the value in this field by the slot power limit value field . 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ro/fwd hwinit/rev no yes 00b 00b 18:17 reserved 00b 31:19 physical slot number forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: specifies a non-zero identification number for the pex 8114 pci express port slot. ro/fwd hwinit/rev no yes 0-0h 0-0h register 14-32. 7ch slot capabilities (reverse transparent bridge mode only) (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 258 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-33. 80h slot status and control (reverse transparent bridge mode only) bit(s) description type serial eeprom default slot control 0 attention button pressed enabled forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = function disabled 1 = enables a hot plug interrupt or wakeup event on an attention button pressed event on the pex 8114 pci express port ro/fwd r/w/rev no ye s 0 0 1 power fault detected enable forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = function disabled 1 = enables a hot plug interrupt or wakeup event on a power fault event on the pex 8114 pci express port ro/fwd r/w/rev no ye s 0 0 2 mrl sensor change enable forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = function disabled 1 = enables a hot plug interrupt or wakeup event on an mrl sensor change event on the pex 8114 pci express port ro/fwd r/w/rev no ye s 0 0 3 presence detect change enable forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = function disabled 1 = enables a hot plug interrupt or wakeup event on a presence detect change event on the pex 8114 pci express port ro/fwd r/w/rev no ye s 0 0
january, 2007 pci expre ss capabilities registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 259 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 4 command completed interrupt enable forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = function disabled 1 = enables a hot plug interrupt or wakeup event when a command is completed by the hot plug controller on the pex 8114 pci express port ro/fwd r/w/rev no ye s 0 0 5 hot plug interrupt enable forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: 0 = function disabled 1 = enables a hot plug interrupt on any enabled hot plug events for the pex 8114 pci express port ro/fwd r/w/rev no ye s 0 0 7:6 attention indicator control forward transparent bridge mode: do not change for forward transparent bridge mode. reverse transparent bridge mode: controls the attention indicator on the pex 8114 pci express port slot. 00b = reserved ? do not use 01b = turns on indicator to constant on state 10b = causes indicator to blink 11b = turns off indicator writes cause the pex 8114 pci express port to transmit the appropriate attention indicator messages. reads return the pex 8114 pci expr ess port attention indicator?s current state. ro/fwd r/w/rev no ye s 00b 11b 9:8 power indicator control forward transparent bridge mode: do not change for forward transparent bridge mode. reverse transparent bridge mode: controls the power indicator on the pex 8114 pci express port slot. 00b = reserved ? do not use 01b = turns on indicator to constant on state 10b = causes indicator to blink 11b = turns off indicator writes cause the pex 8114 pci express port to transmit the appropriate power indicator message. reads return the pex 8114 pci expres s port power indicator?s current state. ro/fwd r/w/rev no ye s 00b 11b 10 power controller control forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: controls the pex 8114 pci express port slot power controller: 0 = turns on power controller 1 = turns off power controller ro/fwd r/w/rev no ye s 0 1 15:11 reserved 0-0h register 14-33. 80h slot status and control (reverse transparent bridge mode only) (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 260 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 slot status 16 attention button pressed forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: set to 1 when the pex 8114 pci express port slot attention button is pressed. ro/fwd r/w1c/rev no ye s 0 0 17 power fault detected forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: set to 1 when the pex 8114 pci expr ess port slot power controller detects a power fault at the slot. ro/fwd r/w1c/rev no ye s 0 0 18 mrl sensor changed forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: set to 1 when an mrl state cha nge is detected on the pex 8114 pci express port slot. ro/fwd r/w1c/rev no ye s 0 0 19 presence detect changed forward transparent bridge mode: not valid for forward transparent bridge mode. reverse transparent bridge mode: set to 1 when a presence detect ch ange is detected on the pex 8114 pci express port slot. ro/fwd r/w1c/rev no ye s 0 0 20 command completed forward transparent bridge mode: do not change for forward transparent bridge mode. reverse transparent bridge mode: set to 1 when the pex 8114 pci express port slot hot plug controller completes an issued command. ro/fwd r/w1c/rev no ye s 0 0 21 mrl sensor state forward transparent bridge mode: do not change for forward transparent bridge mode. reverse transparent bridge mode: reveals the pex 8114 pci express port mrl sensor?s current state. 0 = mrl sensor closed 1 = mrl sensor open ro/fwd ro/rev no ye s 0 0 22 presence detect state forward transparent bridge mode: do not use for forward transparent bridge mode. reverse transparent bridge mode: reveals the pex 8114 pci express port slot?s current state. 0 = slot empty 1 = slot occupied ro/fwd ro/rev no ye s 0 0 31:23 reserved 0-0h register 14-33. 80h slot status and control (reverse transparent bridge mode only) (cont.) bit(s) description type serial eeprom default
january, 2007 plx indirect configuration access mechanism registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 261 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.9 plx indirect configuration access mechanism registers table 14-8. plx indirect configurat ion access mechanism register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 configuration address window f8h configuration data window fch register 14-34. f8h configuration address window bit(s) description type serial eeprom default 2:0 function number [2:0] ro/fwd r/w/rev no no 000b 000b 7:3 device number [4:0] ro/fwd r/w/rev no no 0000_0b 0000_0b 15:8 bus number [7:0] ro/fwd r/w/rev no no 00h 00h 25:16 register dword address [9:0] ro/fwd r/w/rev no no 000h 000h 30:26 reserved 0h 31 configuration enable ro/fwd r/w/rev no no 0 0 register 14-35. fch configuration data window bit(s) description type serial eeprom default 31:0 software selects a register by wr iting into the register address window, write or read that register using data window. ro/fwd r/w/rev no no 0000_0000h 0000_0000h
pex 8114 registers plx technology, inc. 262 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.10 device serial number extended capability registers this section details the pex 8114 device serial number extended capability registers. table 14-9 defines the register map. table 14-9. pex 8114 device serial number extended capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capabi lity offset ( fb4h ) capability ve r s i o n ( 1h ) extended capability id ( 0003h ) 100h serial number (low) 104h serial number (high) 108h register 14-36. 100h device serial number extended capability bit(s) description type serial eeprom default 15:0 extended capability id set to 0003h , as required by the pci express base 1.0a. ro yes 0003h 19:16 capability version set to 1h , as required by the pci express base 1.0a. ro yes 1h 31:20 next capability offset set to fb4h , which is the pci express enhanced capability header registers. ro yes fb4h register 14-37. 104h serial number (low) bit(s) description type serial eeprom default 31:0 serial number[31:0] lower half of a 64-bit register. va lue set by serial eeprom register initialization. ro yes 0000_0edfh register 14-38. 108h serial number (high) bit(s) description type serial eeprom default 31:0 serial number[63:32] upper half of a 64-bit register. valu e set by serial eeprom register initialization. ro yes 0000_0001h
january, 2007 device power budget ing extended capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 263 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.11 device power budgeting extended capability registers this section details the pex 8114 device power budgeting extended capability registers. table 14-10 defines the register map. note: there are eight registers that can be programmed by way of the serial eeprom. each register has a different power configuration for the port. each configuration is selected by writing to the data select register data select bits. table 14-10. pex 8114 device power budget ing extended capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ( 148h ) capability ve r s i o n ( 1h ) ( 0004h ) 138h reserved data select 13ch power data 140h reserved power budget capability 144h register 14-39. 138h device power budgeting extended capability bit(s) description type serial eeprom default 15:0 extended capability id set to 0004h , as required by the pci express base 1.0a. ro yes 0004h 19:16 capability version set to 1h , as required by the pci express base 1.0a. ro yes 1h 31:20 next capability offset set to 148h , which addresses the pex 8114 virtual channel budgeting extended capability registers. ro yes 148h register 14-40. 13ch data select bit(s) description type serial eeprom default 7:0 data select indexes the power budgeting data reported by way of eight power data registers and selects the dword of power budge ting data that appears in each power data register. index values start at 0, to sele ct the first dword of power budgeting data; subsequent dwords of po wer budgeting data are sele cted by increasing index values 1 to 7. r/w yes 00h 31:8 reserved 0000_00h
pex 8114 registers plx technology, inc. 264 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-41. 140h power data bit(s) description type serial eeprom default 7:0 base power four registers. specifies, in watts, the base power value in the operating condition. this value must be multiplied by the data scale to produce the actual power consumption value. ro yes 00h 9:8 data scale specifies the scale to apply to the base power value. the power consumption of the device is determined by multiplying the base power field contents with the value corresponding to the encoding returned by this field. defined encodings are: 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ro yes 00b 12:10 pm sub-state 000b = pex 8114 is in the defaul t power manageme nt sub-state ro yes 000b 14:13 pm state current power state. 00b = d0 state 01b = not used ? d1 state not supported 10b = not used ? d2 state not supported 11b = d3 state ro yes 00b 17:15 type type of operating condition. 000b = pme auxiliary 001b = auxiliary 010b = idle 011b = sustained 111b = maximum all other values are reserved . ro yes 000b 20:18 power rail power rail of operating condition. 000b = power 12v 001b = power 3.3v 010b = power 1.8v 111b = thermal all other values are reserved . ro yes 000b 31:21 reserved 0-0h register 14-42. 144h power budget capability bit(s) description type serial eeprom default 0 system allocated 1 = power budget for the device is in cluded within the system power budget hwinit yes 1 31:1 reserved 0-0h
january, 2007 virtual channel extended capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 265 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.12 virtual channel extended capability registers this section details the pex 8114 pci express virtual channel extended capability registers. table 14-11 defines the register map. table 14-11. pex 8114 virtual channel extended capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 000h ) capability ve r s i o n ( 1h ) extended capability id ( 0002h ) 148h port vc capability 1 14ch port vc capability 2 (not supported) 150h port vc status (not supported) port vc control (not supported) 154h vc0 resource capability (not supported) 158h vc0 resource control 15ch vc0 resource status reserved 160h reserved 164h ? 1c4h register 14-43. 148h virtual channel budgeting extended capability bit(s) description type serial eeprom default 15:0 extended capability id set to 0002h , as required by the pci express base 1.0a . ro yes 0002h 19:16 capability version set to 1h , as required by the pci express base 1.0a . ro yes 1h 31:20 next capability offset set to 000h , indicating that the virtual channe l extended capability is the last extended capability in the extended capability list. ro yes 000h
pex 8114 registers plx technology, inc. 266 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-44. 14ch port vc capability 1 bit(s) description type serial eeprom default 0 extended vc count 0 = pex 8114 supports only the default virtual channel 0 ro no 0 3:1 reserved 000b 4 low-priority extended vc count for strict priority arbitrati on, indicates the num ber of extended virt ual channels (those in addition to the default virtual channel 0) that belong to the low-priority virtual channel group for the pex 8114. 0 = for the pex 8114, only the default virtua l channel 0 belongs to the low-priority virtual channel group ro no 0 7:5 reserved 000b 9:8 reference clocks not supported. cleared to 00b. ro no 00b 11:10 port arbitration table-entry size not supported. cleared to 00b. ro no 00b 31:12 reserved 0-0h register 14-45. 150h port vc capability 2 bit(s) description type serial eeprom default 1:0 vc arbitration capabilities not supported. cleared to 00b. ro no 00b 23:2 reserved 0-0h 31:24 vc arbitration table offset not supported. cleared to 00h. ro no 00h register 14-46. 154h port vc status and control bit(s) description type serial eeprom default port vc control 0 load vc arbitration table not supported. cleared to 0. ro no 0 1 vc arbitration select not supported. cleared to 0. ro no 0 15:2 reserved 0-0h port vc status 16 vc arbitration table status not supported. cleared to 0. ro no 0 31:17 reserved 0-0h
january, 2007 virtual channel extended capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 267 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-47. 158h vc0 resource capability bit(s) description type serial eeprom default 0 port arbitration capability not supported. cleared to 0. ro no 0 13:1 reserved 0-0h 14 advanced packet switching not supported. cleared to 0. ro no 0 15 reject snoop transactions not supported. cleared to 0. ro no 0 22:16 maximum time slots not supported. cleared to 000_0000b. ro no 000_0000b 23 reserved 0 31:24 port arbitration table offset not supported. cleared to 00h. ro no 00h register 14-48. 15ch vc0 resource control bit(s) description type serial eeprom default 0 tc/vc0 map the pex 8114 supports only vc0. traffic class 0 (tc0) must be mapped to virtual channel 0. by default, traffic classe s [7:1] are mapped to vc0. ro yes ffh 7:1 r/w yes 15:8 reserved 00h 16 load port arbitration table not supported. cleared to 0. ro no 0 19:17 port arbitration select not supported. cleared to 000b. ro no 000b 23:20 reserved 0-0h 26:24 vc0 id defines the pex 8114 pci express virtual channel 0 id code. because this is the default vc 0, it is cleared to 000b. ro yes 000b 30:27 reserved 0-0h 31 vc0 enable 0 = not allowed 1 = enables pex 8114 pci expres s default virtual channel 0 ro yes 1
pex 8114 registers plx technology, inc. 268 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-49. 160h vc0 resource status bit(s) description type serial eeprom default 15:0 reserved 0000h 16 port arbitration table status not supported. cleared to 0. ro no 0 17 vc0 negotiation pending 0 = vc0 negotiation completed 1 = vc0 initialization is not comple te for the pex 8114 pci express link ro yes 1 31:18 reserved 0-0h
january, 2007 plx-specific registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 269 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13 plx-specific registers the registers described in this section are uniqu e to the pex 8114 device, are not referenced in the pci express base 1.0a , and pertain to the pci express interface. table 14-12 defines the register map. note: in reverse transparent bridge mode, this register gr oup is accessed using a memory-mapped cycle or the plx indirect configuration access mechanism. it is recommended that these register values not be changed. table 14-12. plx-specific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 error checking and debug registers 1c8h ? 1f8h physical layer registers 210h ? 2c4h cam routing registers 2c8h ? 6bch base address registers (bars) 6c0h ? 73ch ingress credit handler (inch) registers 9f4h b7ch internal credit handler (itch ) vc&t threshold registers c00h ? c10h f70h ? f7ch
pex 8114 registers plx technology, inc. 270 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.1 error checking and debug registers table 14-13. plx-specific error checking and debug register map (pci express interface) a a. certain registers are station-specific, while others are device-specific. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ecc check disable 1c8h reserved device-specific error 32-bit erro r status (factory test only) 1cch reserved device-specific error 32-bit erro r mask (factory test only) 1d0h reserved 1d4h ? 1dch power management hot pl ug user configuration 1e0h egress control and status 1e4h reserved bad tlp count 1e8h reserved bad dllp count 1ech tlp payload length count 1f0h reserved 1f4h reserved ack transmission latency limit 1f8h register 14-50. 1c8h ecc check disable bit(s) description type serial eeprom default 0 ecc 1-bit error check disable 0 = ram 1-bit soft error check enabled 1 = disables ram 1-bit soft error check r/w yes 0 1 ecc 2-bit error check disable 0 = ram 2-bit soft error check enabled 1 = disables ram 2-bit soft error check r/w yes 0 31:2 reserved 0-0h
january, 2007 error checking and debug registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 271 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 note: all errors in register offset 1cch generate msi/inta# interrupts, if enabled. register 14-51. 1cch device-specific error 32-bit error status (factory test only) bit(s) description type serial eeprom default 0 device-specific error completion fifo overflow status 0 = no overflow detected 1 = completion fifo overflow de tected when 4-deep completion fifo for ingress, or 2-deep comp letion fifo for egress, overflows r/w1cs yes 0 1 egress pram soft error overflow egress packet ram 1-bit soft error counter overflow. 0 = no error detected 1 = egress pram 1-bit soft error (8-bit counter) overflow when destination packet ram 1-bit soft e rror count is greater than or equal to 256, it generates an msi/ inta# interrupt, if enabled r/w1cs yes 0 2 egress llist soft error overflow egress link-list ram 1-bit soft error counter overflow. 0 = no error detected 1 = egress link-list 1-bit soft e rror (8-bit counter) overflow when destination module link lists ram 1- bit soft error count is greater than or equal to 256, it generates an msi/inta# interrupt, if enabled r/w1cs yes 0 3 egress pram ecc error egress packet ram 2-bit error detection. 0 = no error detected 1 = egress pram 2-bit ecc error detected r/w1cs yes 0 4 egress llist ecc error egress link-list ram 2-bit error detection. 0 = no error detected 1 = egress link-list 2-bit ecc error detected r/w1cs yes 0 5 ingress ram 1-bit ecc error source packet ram 1-bit soft error detection. 0 = no error detected 1 = ingress ram 1-bit ecc error detected r/w1cs yes 0 6 egress memory allocation unit (mau) 1-bit soft error counter overflow egress memory allocati on/de-allocation ram 1- bit soft error count is greater than or equal to 8. 0 = no error detected 1 = egress mau 1-bit soft error overflow r/w1cs yes 0 7 egress memory allocation unit (mau) 2-bit soft error egress packet memory allocati on/de-allocation ram 2-bit error detection. 0 = no 2-bit error detected 1 = egress mau 2-bit soft error detected r/w1cs yes 0
pex 8114 registers plx technology, inc. 272 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8 ingress ram uncorrectable ecc error ingress packet ram 2-bit error detection. 0 = no 2-bit error detected 1 = packet ram uncorrectable ecc error detected r/w1cs yes 0 9 ingress llist 1-bit ecc error ingress link-list ram 1-bi t soft error detection. 0 = no error detected 1 = 1-bit ecc error detected r/w1cs yes 0 10 ingress llist uncorrectable ecc error ingress packet link-list ram 2-bit error detection. 0 = no 2-bit error detected 1 = ingress link-list uncorre ctable ecc error detected r/w1cs yes 0 11 credit update timeout status no useful credit update to make forward progress for 512 ms or 1s (disabled by default). 0 = no credit update timeout detected 1 = credit update timeout completed r/w1cs yes 0 12 inch underrun error ingress credit underrun. 0 = no error detected 1 = credit underrun error detected r/w1cs yes 0 13 ingress memory allocation un it 1-bit soft error counter overflow ingress memory allocation/de-all ocation ram 1-bit soft error count greater than or equal to 8. 0 = no error detected 1 = 1-bit soft error counter is > 8 r/w1cs yes 0 14 ingress memory allocation unit 2-bit soft error ingress memory alloca tion/de-allocation ram 2-bit error detection for transaction layer ingress memory allocation/de-allocation unit. 0 = no error detected 1 = 2-bit soft error detected r/w1cs yes 0 31:15 reserved 0-0h register 14-51. 1cch device-specific error 32-bit error status (factory test only) (cont.) bit(s) description type serial eeprom default
january, 2007 error checking and debug registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 273 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-52. 1d0h device-specific error 32-bit error mask (factory test only) bit(s) description type serial eeprom default 0 device-specific error completion fifo overflow status mask 0 = when enabled, error ge nerates msi/inta# interrupt 1 = device-specific error comple tion fifo overflow status bit is masked/disabled r/ws yes 1 1 egress pram soft error overflow mask 0 = no effect on reporting activity 1 = egress pram soft error overflow bit is masked/disabled r/ws yes 1 2 egress llist soft error overflow mask 0 = no effect on reporting activity 1 = egress llist soft error overflow bit is masked/disabled r/ws yes 1 3 egress pram ecc error mask 0 = no effect on reporting activity 1 = egress pram ecc error bit is masked/disabled r/ws yes 1 4 egress llist ecc error mask 0 = no effect on reporting activity 1 = egress llist ecc error bit is masked/disabled r/ws yes 1 5 ingress ram 1-bit ecc error mask 0 = no effect on reporting activity 1 = ingress ram 1-bit ecc error bit is masked/disabled r/ws yes 1 6 egress memory allocation unit 1-bit soft error counter overflow mask 0 = no effect on reporting activity 1 = egress memory allocation unit (mau) 1-bit soft error counter overflow bit is masked/disabled r/ws yes 1 7 egress memory allocation unit 2-bit soft error mask 0 = no effect on reporting activity 1 = egress memory allocation unit (mau) 2-bit soft error bit is masked/disabled r/ws yes 1 8 ingress ram uncorrectable ecc error mask 0 = no effect on reporting activity 1 = ingress ram uncorrectable ecc error bit is masked/disabled r/ws yes 1 9 ingress llist 1-bit ecc error mask 0 = no effect on reporting activity 1 = ingress ram 1-bit ecc error bit is masked/disabled r/ws yes 1 10 ingress llist uncorrectable ecc error mask 0 = no effect on reporting activity 1 = ingress llist uncorrectable ecc error bit is masked/disabled r/ws yes 1 11 credit update timeout status mask 0 = no effect on reporting activity 1 = credit update timeout status bit is masked/disabled r/ws yes 1
pex 8114 registers plx technology, inc. 274 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 12 inch underrun error mask 0 = no effect on reporting activity 1 = inch underrun error bit is masked/disabled r/ws yes 1 13 ingress memory allocation unit 1-bit soft error counter overflow mask 0 = no effect on reporting activity 1 = tic_mau 1-bit soft error counter-overflow is masked/disabled r/ws yes 1 14 ingress memory allocation unit 2-bit soft error mask 0 = error reporting enabled using interrupts 1 = 2-bit soft error repor ting is masked/disabled r/ws yes 1 31:15 reserved 0-0h register 14-53. 1e0h power management hot plug user configuration bit(s) description type serial eeprom default 0 l0s entry idle count time to meet to enter l0s. 0 = idle condition lasts for 1 s 1 = idle condition lasts for 4 s r/w yes 0 1 l1 upstream port receiver idle count for active l1 entry. 0 = upstream port receiver idle for 2 s 1 = upstream port receiver idle for 3 s r/w yes 0 2 hpc pme turn-off enable 1 = pme turn-off message is transmitted before the port is turned off on downstream port r/w yes 0 4:3 hpc t pepv delay slot power-applied to power-valid delay time. 00b = 16 ms 01b = 32 ms 10b = 64 ms 11b = 128 ms ro yes 00b 5 hpc inband presence detect enable 0 = hp_prsnt# input ball used to detect a boa rd present in the slot 1 = serdes receiver detect mechanism is used to detect a board present in the slot ro yes 0 6 hpc t pvperl delay downstream port power-valid to reset signal release time. 0 = 20 ms 1 = 100 ms ro yes 1 12:7 hpc test bits factory test only. testing bits ? must be 0_0000_0b. r/w yes 0_0000_0b 31:13 reserved 0-0h register 14-52. 1d0h device-specific error 32-bit error mask (factory test only) (cont.) bit(s) description type serial eeprom default
january, 2007 error checking and debug registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 275 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-54. 1e4h egress control and status bit(s) description type serial eeprom default 0 egress credit u pdate timer enable in this mode, when the port is not rece iving credits to make forward progress and the egress timeout time r times out, the downstre am link is brought down. 0 = egress credit update time r disabled 1 = egress credit update timer enabled r/w yes 0 1 egress timeout value 0 = minimum 512 ms (maximum 768 ms) 1 = minimum 1,024 ms (maximum 1,280 ms) r/w yes 0 2 dl_down handling 0 = reports unsupported request error for all tl p requests received in dl_down state 1 = reports unsupported request for first posted/non-po sted tlp request in dl_down state ? silently dr ops subsequent tlp requests r/w yes 0 7:3 reserved 0-0h 15:8 link-list ram soft error count link-list ram 8-bit soft error c ounter value. counter shared by: packet link-list ram packet link-list de-allocation ram scheduler data ram counter increments for 1-bit soft errors detected in any of these ram. ro yes 00h 19:16 vc&t encountered timeout 0h = vc0 posted 1h = vc0 non-posted 2h = vc0 completion all other values are not supported . ro yes 0h 23:20 reserved 0h 31:24 packet ram soft error count counter increments for each 1-bit soft error detected in ram. ro no 00h register 14-55. 1e8h bad tlp count bit(s) description type serial eeprom default 7:0 bad tlp count counts number of tlps with bad lcrc, or number of tlps with a sequence number mismatch error. the maximum value is ffh. r/w yes 00h 31:8 reserved 0000_00h register 14-56. 1ech bad dllp count bit(s) description type serial eeprom default 7:0 bad dllp count counts number of dllps with bad lcrc, or number of dllps with a sequence number mismatch error. the maximum value is ffh. r/w yes 00h 31:8 reserved 0000_00h
pex 8114 registers plx technology, inc. 276 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-57. 1f0h tlp payload length count bit(s) description type serial eeprom default 20:0 tlp payload length count defines the tlp payload size transf erred over the link in 1-ms period. r/w yes 00_0000h 31:21 reserved 000h register 14-58. 1f8h ack transmission latency limit bit(s) description type serial eeprom default 7:0 ack transmission latency limit value based on the negotiated link width encoding: r/w yes ffh 15:8 hpc test bits factory test only. testing bits ? must be 00h. r/w yes 00h 31:16 reserved 0000h link width register value decimal hex x1 255 ffh x2 217 d9h x4 118 76h
january, 2007 physical layer registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 277 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.2 physical layer registers note: in this section, the term ?serdes quad? or ?quad? refers to assembling serdes lanes into a group of four contiguous lanes for testing purposes. the quad is defined as serdes[0-3]. table 14-14. plx-specific physical layer register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 test pattern_0 210h test pattern_1 214h test pattern_2 218h test pattern_3 21ch physical layer status ph ysical layer control 220h port configuration 224h physical layer test 228h physical layer (factory test only) 22ch physical layer port command 230h skip ordered-set interval 234h quad serdes[0-3] diagnostics data 238h reserved 23ch ? 244h reserved serdes nominal drive cur- rent select 248h reserved serdes drive current level_1 24ch reserved 250h reserved serdes drive equalization level select_1 254h reserved 258h ? 25ch status data from serial eeprom serial eeprom status serial eeprom control 260h serial eeprom buffer 264h reserved 268h ? 2c4h
pex 8114 registers plx technology, inc. 278 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-59. 210h test pattern_0 bit(s) description type serial eeprom default 31:0 test pattern_0 used for digital far- end loop-back testing. r/w yes 0-0h register 14-60. 214h test pattern_1 bit(s) description type serial eeprom default 31:0 test pattern_1 used for digital far- end loop-back testing. r/w yes 0-0h register 14-61. 218h test pattern_2 bit(s) description type serial eeprom default 31:0 test pattern_2 used for digital far- end loop-back testing. r/w yes 0-0h register 14-62. 21ch test pattern_3 bit(s) description type serial eeprom default 31:0 test pattern_3 used for digital far-end loop-back testing. r/w yes 0-0h
january, 2007 physical layer registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 279 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-63. 220h physical layer status and control bit(s) description type serial eeprom default physical layer control 0 port enumerator enable 0 = enumerate not enabled 1 = enumerate enabled hwinit yes 0 1 tdm enable 0 = tdm not enabled 1 = tdm enabled hwinit yes 0 2 reserved 0 3 upstream port as conf iguration master enable 0 = upstream port cross-link not supported 1 = upstream port cross-link supported r/w yes 0 4 downstream port as configuration slave enable 0 = downstream port cross-link not supported 1 = downstream port cross-link supported r/w yes 0 5 lane reversal disable 0 = lane reversal supported 1 = lane reversal not supported r/w yes 0 6 reserved 0 7 fc-init triplet enable flow control initialization. 0 = init fl1 triplet can be interrupted by skip ordered-set/idle data symbol 1 = init fl1 triplet not interrupted r/w yes 0 15:8 n_fts value n_fts value to transmit in training sets. r/w yes 40h physical layer status 19:16 reserved 0h 22:20 number of ports enumerated number of ports in current configuration. hwinit yes 000b 23 reserved 0 24 port 0 deskew buffer error status 1 = deskew buffer overflow or underflow r/w1c yes 0 31:25 reserved 00h register 14-64. 224h port configuration bit(s) description type serial eeprom default 2:0 port configuration hwinit yes 000b 31:3 reserved 0-0h
pex 8114 registers plx technology, inc. 280 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-65. 228h physical layer test bit(s) description type serial eeprom default 0 timer test mode enable 0 = standard physical la yer timer parameters used 1 = shortens timer scale fro m milliseconds to microseconds r/w yes 0 1 skip-timer test mode enable 0 = disables skip-timer test mode 1 = enables skip-timer test mode r/w yes 0 2 port_0_x1 1 = pci express interface is configured as x1 r/w yes 0 3 tcb capture disable 0 = training control bit (tcb) capture enabled 1 = disables tcb capture r/w yes 0 4 analog loop-back enable 1 = analog loop-back testing enabled (loop-back before elastic buffer) r/w yes 0 5 port/serdes test pattern enable select 1 = test pattern enable bits select the port, rather than serdes[0-3] r/w yes 0 6 reserved 0 7 serdes bist enable when programmed to 1 by the serial eeprom, enables serdes internal loop-back p rbs test for 512 s before starting link initialization. ro yes 0 9:8 prbs association selects the serdes within the quad for prbs generation/checking. value selects pci express station serdes 00b = 0 01b = 1 10b = 2 11b = 3 r/w yes 00b 15:10 reserved 0-0h
january, 2007 physical layer registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 281 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 16 prbs enable when set to 1, enables prbs sequence generation/checking on serdes[0-3]. r/w yes 0 19:17 reserved 000b 20 prbs external loop-back the following bit commands are va lid when the loop-back command is enabled in offset 230h . 0 = serdes[0-3] establishes internal analog loop-back when bit 16=1 1 = serdes[0-3] establishes extern al analog loop-back when bit 16=1 r/w yes 0 23:21 reserved 000b 24 prbs error count reset when set to 1, resets the prbs error counter (offset 238h [31:24]). ro yes 0 27:25 reserved 000b 28 test pattern enable enables serdes[0-3] test pattern transmission in digital far-end loop-back mode. r/w yes 0 31:29 reserved 000b register 14-66. 22ch physical layer (factory test only) bit(s) description type serial eeprom default 31:0 factory test only r/w yes 0-0h register 14-65. 228h physical layer test (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 282 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-67. 230h physical layer port command bit(s) description type serial eeprom default 0 port 0 loop-back 0 = pci express interface not enabled to proceed to loop-back state 1 = pci express interface enabled to proceed to loop-back state r/w yes 0 1 port 0 scrambler disable when serial eeprom load sets this bit, scrambler is disabled in configuration-complete state. when software sets this bit when th e link is in the up state, hardware immediately disables it s scrambler without executing link training protocol. the upstream/downstream de vice scrambler is not disabled. 0 = pci express interface scrambler enabled 1 = pci express interface scrambler disabled r/w yes 0 2 port 0 rx l1 only pci express interface receiver enters aspm l1. 0 = pci express interface receiver allowed to proceed to aspm l0s or l1 state when it detects electric al idle ordered-set in l0 state 1 = pci express interface receiver allowed to proceed to aspm l1 only when it detects electrical idle ordered-set in l0 state r/w yes 0 3 port 0 ready as loop-back master pci express interface ltssm esta blished loop-back as a master. 0 = pci express interface no t in loop-back master mode 1 = pci express interface in loop-back master mode ro no 0 31:4 reserved 0000_000h register 14-68. 234h skip ordered-set interval bit(s) description type serial eeprom default 11:0 skip ordered-set interval skip ordered-set interv al (in symbol times). r/ws yes 49ch 31:12 reserved 0000_0h
january, 2007 physical layer registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 283 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-69. 238h quad serdes[0-3] diagnostics data bit(s) description type serial eeprom default 9:0 expected prbs data expected prbs serdes [0-3] diagnostic data. ro yes 000h 19:10 received prbs data received prbs serdes[0-3] diagnostic data. ro yes 000h 23:20 reserved 0h 31:24 prbs error count prbs serdes[0-3] erro r count (0 to 255). ro yes 00h register 14-70. 248h serdes nominal drive current select bit(s) description type serial eeprom default 1:0 serdes_0 nominal drive current the following values for nominal current apply to each drive: 00b = 20 ma 01b = 10 ma 10b = 28 ma 11b = 20 ma r/ws yes 00b 3:2 serdes_1 nominal drive current r/ws yes 00b 5:4 serdes_2 nominal drive current r/ws yes 00b 7:6 serdes_3 nominal drive current r/ws yes 00b 31:8 reserved 0000_00h register 14-71. 24ch serdes drive current level_1 bit(s) description type serial eeprom default 3:0 serdes_0 drive current level the following values represent the ratio of actual current/ nominal current (selected in serdes nominal drive current select register) and apply to each drive: r/ws yes 0h 7:4 serdes_1 drive current level r/ws yes 0h 11:8 serdes_2 drive current level r/ws yes 0h 15:12 serdes_3 drive current level r/ws yes 0h 31:16 reserved 0000h 0h = 1.00 1h = 1.05 2h = 1.10 3h = 1.15 4h = 1.20 5h = 1.25 6h = 1.30 7h = 1.35 8h = 0.60 9h = 0.65 ah = 0.70 bh = 0.75 ch = 0.80 dh = 0.85 eh = 0.90 fh = 0.95
pex 8114 registers plx technology, inc. 284 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-72. 254h serdes drive equalization level select_1 bit(s) description type serial eeprom default 3:0 serdes_0 drive equalization level the following values represent the percentage of drive current attributable to equalization curre nt and apply to each drive: r/ws yes 8h 7:4 serdes_1 drive equalization level r/ws yes 8h 11:8 serdes_2 drive equalization level r/ws yes 8h 15:12 serdes_3 drive equalization level r/ws yes 8h 31:16 reserved 0000h i eq / i dr de-emphasis (db) 0h = 0.00 1h = 0.04 2h = 0.08 3h = 0.12 4h = 0.16 5h = 0.20 6h = 0.24 7h = 0.28 8h = 0.32 9h = 0.36 ah = 0.40 bh = 0.44 ch = 0.48 dh = 0.52 eh = 0.56 fh = 0.60 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96
january, 2007 physical layer registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 285 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-73. 260h serial eeprom status and control bit(s) description type serial eeprom default serial eeprom control 12:0 serial eeprom block address serial eeprom block address for 32 kb. r/w yes 0000h 15:13 serial eeprom command commands to the serial eeprom controller. 001b = data from serial eeprom st atus[31:24] bits written to the serial eeprom internal status register 010b = write four bytes of data from the serial eeprom buffer into memory location pointed to by the serial eeprom block address field 011b = read four bytes of data from memory location pointed to by the serial eeprom block address field into the serial eeprom buffer 100b = reset write enable latch 101b = data from serial ee prom internal status re gister written to the serial eeprom status[31:24] bits 110b = set write enable latch all other values are reserved . r/w yes 000b serial eeprom status 17:16 serial eeprom present serial eeprom present status. 00b = not present 01b = serial eeprom present ? no crc error 10b = reserved 11b = serial eeprom present, but w ith crc error ? default reset value used ro yes 00b 19:18 serial eeprom command status 00b = serial eeprom command complete 01b = serial eeprom command not complete 10b = serial eeprom command complete with crc error 11b = reserved ro yes 00b 20 serial eeprom block address upper bit serial eeprom block address upper bit 13. extends serial eeprom to 64 kb. r/w yes 0 21 crc disable 0 = serial eeprom input data uses crc 1 = serial eeprom i nput data crc disabled r/w yes 0 23:22 reserved 00b
pex 8114 registers plx technology, inc. 286 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 status data from serial eeprom 24 serial eeprom_rdy# 0 = serial eeprom ready to transmit data 1 = write cycle in progress r/w yes 0 25 serial eeprom_wen 0 = serial eeprom write disabled 1 = serial eeprom write enabled r/w yes 0 27:26 serial eeprom_bp[1:0] serial eeprom block-write protect bits. r/w yes 00b 30:28 serial eeprom write status value is 000b when serial eeprom is not in an internal write cycle. ro yes 000b 31 serial eeprom_wpen serial eeprom write protect enable. when: = 0 and serial eeprom_wen = 1, the serial eeprom status register is writable. = 1, serial eeprom status register is protected. r/w yes 0 register 14-74. 264h serial eeprom buffer bit(s) description type serial eeprom default 31:0 serial eeprom buffer r/w no 0-0h register 14-73. 260h serial eeprom status and control (cont.) bit(s) description type serial eeprom default bp[1:0] level array addresses protected 16-kb device 32-kb device 64-kb device 00b 0 none none none 01b 1 (1/4) 3000h - 3fffh 6000h - 7fffh c000h - ffffh 10b 2 (1/2) 2000h - 3fffh 4000h - 7fffh 8000h - ffffh 11b 3 (all) 0000h - 3fffh 0000h - 7fffh 0000h - ffffh
january, 2007 cam routing registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 287 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.3 cam routing registers the cam routing registers contain mirror copies of the registers used for: bus number cam (content-addressable memory) ? used to determine configuration tlp completion route this register contains a mi rror copy of the pex 8114 primary bus number , secondary bus number , and subordinate bus number registers. i/o cam ? used to determine i/o request routing this register contains a mirror copy of the pex 8114 i/o base and i/o limit registers. amcam (address-mapping cam) ? used to determine memory request route these registers contain mirr or copies of the pex 8114 memory base and limit address , prefetchable memory ba se and limit address , and prefetchable memory upper base address[63:32] and prefetchable memory upper limit address[63:32] registers. these registers are automatically updated by hardware. modifying these registers by writing to the addresses listed herein is not reco mmended. these mirror copies are used by the pci express interface. table 14-15. plx-specific cam routing register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 2c8h ? 2e4h bus number cam 8 2e8h reserved 2ech ? 314h reserved i/o cam_8 318h reserved 31ch ? 3c4h amcam_8 memory limit and base 3c8h amcam_8 prefetchable memory limit and base[31:0] 3cch amcam_8 prefetchable memory base[63:32] 3d0h amcam_8 prefetchable memory limit[63:32] 3d4h reserved 3d8h ? 65ch tic control 660h reserved 664h tic port enable (factory test only) 668h reserved 66ch ? 69ch iocam_8 limit[31:16] io cam_8 base[31:16] 6a0h reserved 6a4h ? 6bch
pex 8114 registers plx technology, inc. 288 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.3.1 bus number cam register 14.13.3.2 i/o cam register register 14-75. 2e8h bus number cam 8 bit(s) description type serial eeprom default 7:0 primary bus number mirror copy of primary bus number . r/w yes 00h 15:8 secondary bus number mirror copy of secondary bus number . r/w yes ffh 23:16 subordinate bus number mirror copy of subordinate bus number . r/w yes 00h 31:24 reserved 00h register 14-76. 318h i/o cam_8 bit(s) description type serial eeprom default 3:0 i/o addressing capability 1h = 32-bit i/o addressing all other values are reserved . ro yes 1h 7:4 i/o base mirror copy of i/o base value. r/w yes fh 11:8 i/o addressing capability 1h = 32-bit i/o addressing all other values are reserved . ro yes 1h 15:12 i/o limit mirror copy of i/o limit value. r/w yes 0h 31:16 reserved 0000h
january, 2007 cam routing registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 289 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.3.3 amcam (address- mapping cam) registers amcam registers contain mirror images of the pex 8114 memory base and limit address , prefetchable memory base and limit address , and prefetchable memory upper base address[63:32] and prefetchable memory upper limit address[63:32] registers. register 14-77. 3c8h amcam_8 memory limit and base bit(s) description type serial eeprom default 3:0 reserved 0h 15:4 memory base mirror copy of memory base value. r/w yes fffh 19:16 reserved 0h 31:20 memory limit mirror copy of memory limit value. r/w yes 000h register 14-78. 3cch amcam_8 prefetchable memory limit and base[31:0] bit(s) description type serial eeprom default 3:0 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 15:4 prefetchable memory base amcam_8 prefetchable memory base[31:20]. r/w yes fffh 19:16 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 31:20 prefetchable memory limit amcam_8 prefetchable memory limit[31:20]. r/w yes 000h register 14-79. 3d0h amcam_8 prefetchable memory base[63:32] bit(s) description type serial eeprom default 31:0 prefetchable memory base[63:32] amcam_8 prefetchable memory base[63:32]. r/w yes ffff_ffffh register 14-80. 3d4h amcam_8 prefetchable memory limit[63:32] bit(s) description type serial eeprom default 31:0 prefetchable memory limit[63:32] amcam_8 prefetchable memory limit[63:32]. r/w yes 0-0h
pex 8114 registers plx technology, inc. 290 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.3.4 tic control registers table 14-16. plx-specific tic control register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 tic control 660h reserved 664h tic port enable (factory test only) 668h register 14-81. 660h tic control bit(s) description type serial eeprom default 0 tic control valid in reverse transparent bri dge mode. enable s configuration transactions from the downstream port. peer configuration access. wh en set to 1, configuration transactions (type 0) coming upst ream from a downstream port are allowed to enter the device and the type 1 header of the bridge is accessible. r/w yes 0 1 disable unsupported request response for reserved configuration registers r/w yes 0 31:2 tic control factory test only r/w yes 0-0h register 14-82. 668h tic port enable ( factory test only ) bit(s) description type serial eeprom default 31:0 tic_unp_status fac tor y te st on ly r/w yes ffff_ffffh
january, 2007 cam routing registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 291 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.3.5 i/o cam base and limit upper 16 bits registers table 14-17. plx-specific i/o cam base and limit upper 16 bits register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 66ch ? 69ch iocam_8 limit[31:16] io cam_8 base[31:16] 6a0h reserved 6a4h ? 6bch register 14-83. 6a0h i/ocam_8 base and limit upper 16 bits bit(s) description type serial eeprom default 15:0 iocam_8 base[31:16] i/o base upper 16 bits. r/w yes ffffh 31:16 iocam_8 limit[31:16] i/o limit upper 16 bits. r/w yes 0000h
pex 8114 registers plx technology, inc. 292 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.4 base address registers (bars) the registers defined in table 14-18 contain a shadow copy of the two pex 8114 type 1 configuration base address registers. table 14-18. plx-specific base address register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 6c0h ? 6fch bar0_8 700h bar1_8 704h reserved 708h ? 73ch register 14-84. 700h bar0_8 bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar 1 = i/o bar reads 0, and ignores writes. only value of 0 is allowed. ro no 0 2:1 memory mapping range 00b = 32 bits 10b = 64 bits 01b, 11b = reserved r/w yes 00b 3 prefetchable 0 = not prefetchable 1 = prefetchable reads 0, and ignores writes. ro no 0 12:4 reserved 000h 31:13 base address_0 shadow copy of base address 0. where bar0[12:4] = reserved . r/w yes 0000h register 14-85. 704h bar1_8 bit(s) description type serial eeprom default 31:0 base address_1[63:32] when bar0[2:1] = 10b, becomes a shadow copy of base address_1[63:32]. r/w yes 0000_0000h
january, 2007 ingress credit handler (inch) registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 293 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.5 ingress credit ha ndler (inch) registers table 14-19. plx-specific ingress credit handler (inch) register map for pci express interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved inch fc update pending timer 9f4h reserved 9f8h reserved inch mode 9fch inch threshold vc0 posted a00h inch threshold vc0 non-posted a04h inch threshold vc0 completion a08h reserved a0ch ? b7ch register 14-86. 9f4h inch fc update pending timer bit(s) description type serial eeprom default 7:0 update timer update pending time r, using the guidelines as follows. r/w yes 00h 31:8 reserved 0000_00h register 14-87. 9fch inch mode bit(s) description type serial eeprom default 7:0 maximum mode enable factory test only ro yes ffh 15:8 reserved 00h 19:16 factory test only r/w yes 0h 23:20 pending timer source pending timer register ? uses serial eeprom values. r/w yes 0h 31:24 reserved 00h maximum packet size link width default timer count 128 bytes x1 76h x2 40h x4 24h 256 bytes x1 d0h x2 6ch x4 3bh
pex 8114 registers plx technology, inc. 294 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.5.1 inch threshold vi rtual channel registers there are three ingress credit handler (inch) thre shold vc0 registers. thes e registers represent the maximum number of headers or payload credits al located to virtual channel 0, for each type of transaction. the register names a nd address/location are defined in table 14-19 . the following registers describe the data that applies to these registers. register 14-88. a00h inch threshold vc0 posted bit(s) description type serial eeprom default 2:0 reserved 000b 8:3 payload payload = 0_0111_0b. r/w yes 30eh 13:9 header header = 01_100b. 31:14 reserved 0-0h register 14-89. a04h inch threshold vc0 non-posted bit(s) description type serial eeprom default 8:0 payload payload = 0_0000_1010b. r/w yes 140ah 13:9 header header = 01_010b. 31:14 reserved 0-0h register 14-90. a08h inch threshold vc0 completion bit(s) description type serial eeprom default 2:0 reserved 000b 8:3 payload payload = 0_0110_0b. r/w yes 28ch 13:9 header header = 01_010b. 31:14 reserved 0-0h
january, 2007 internal credit handler (itch) vc&t threshold registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 295 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.6 internal credit handler (itch) vc&t threshold registers 14.13.6.1 pci express interface plx- specific internal credit handler (itch) vc&t threshold registers the registers defined in table 14-20 control internal tra ffic from the pci express interface to the pci-x interface. the threshold (packet coun t) units are equivalent to 8 beat s, where each beat can be up to 20 bytes. therefore, a programmed va lue of 1 represents 160 bytes, 2 represents 320 bytes, and so forth. the entire tlp (header, payload, and ecrc, if any) is used to determine a total byte size, and the total byte size is divided by 20 and rounded up to the nearest integer to ascertain the number of beats. every 8 beats counts as 1 threshold unit. the upper packet count is the high threshold. if more units than the programmed upper count are queued, no further packets can be scheduled across the internal fabric. note: previously scheduled packets arrive in their entirety, completely unaffected by the cut-off signal. the lower packet count is the low threshold. af ter cutting off a vc&t due to the high threshold, when the count returns below the low thres hold, that vc&t is again turned on. the upper and lower counts must be different, and the upper number mu st be at least two units larger than the lower number. table 14-20. pex 8114 pci express interface plx-specific internal credit handler (itch) vc&t threshold register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci express interface pci e xpress itch vc&t threshold_1 c00h pci express interface itch vc&t threshold_2 c04h reserved c08h ? c10h
pex 8114 registers plx technology, inc. 296 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 note: although the pex 8114 supports only vc0, the vc1 posted credit fields are used for internal transactions, such as shadow writes. register 14-91. c00h pci express interface pci express itch vc&t threshold_1 bit(s) description type serial eeprom default 4:0 vc0 posted upper packet count vc0 posted upper pa cket beat limit. r/w yes 10h 7:5 not used r/w yes 000b 12:8 vc0 posted lower packet count vc0 posted lower packet beat limit. r/w yes 08h 15:13 not used r/w yes 000b 20:16 vc0 non-posted upper packet count vc0 non-posted upper packet be at limit. r/w yes 04h 23:21 not used r/w yes 000b 28:24 vc0 non-posted lower packet count vc0 non-posted lower packet beat limit. r/w yes 01h 31:29 not used r/w yes 000b register 14-92. c04h pci express interface itch vc&t threshold_2 bit(s) description type serial eeprom default 4:0 vc0 completion upper packet count vc0 completion upper pa cket beat limit. r/w yes 10h 7:5 not used r/w yes 000b 12:8 vc0 completion lower packet count vc0 completion lower packet beat limit. r/w yes 08h 15:13 not used r/w yes 000b 20:16 vc1 posted upper packet count vc1 posted upper packet beat limit. th is information is listed for internal and serial eeprom config uration only ? not to be changed by users. r/w yes 04h 23:21 not used r/w yes 000b 28:24 vc1 posted lower packet count vc1 posted lower packet beat limit. this information is listed for internal and serial eeprom config uration only ? not to be changed by users. r/w yes 01h 31:29 not used r/w yes 000b
january, 2007 internal credit handler (itch) vc&t threshold registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 297 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.13.6.2 pci-x interface plx-specific internal credit handler (itch) vc&t threshold registers the registers defined in table 14-21 control internal traffic from the pci-x interface to the pci express interface. the threshold (packet coun t) units are equivalent to 8 beat s, where each beat can be up to 20 bytes. therefore, a programmed va lue of 1 represents 160 bytes, 2 represents 320 bytes, and so forth. the entire tlp (header, payload, and ecrc, if any) is used to determine a total byte size, and the total byte size is divided by 20 and rounded up to the nearest integer to ascertain the number of beats. every 8 beats counts as 1 threshold unit. the upper packet count is the high threshold. if more units than the programmed upper count are queued, no further packets can be scheduled across the internal fabric. note: previously scheduled packets arrive in their entirety, completely unaffected by the cut-off signal. the lower packet count is the low threshold. af ter cutting off a vc&t due to the high threshold, when the count returns below the low thre shold, that vc&t is again turned on. the upper and lower counts must be different, and the upper number mu st be at least two units larger than the lower number. table 14-21. pex 8114 pci-x interface plx-specific internal credit handler (itch) vc&t threshold register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci-x interface itch vc&t threshold_1 f70h pci-x interface itch vc&t threshold_2 f74h reserved f78h ? f7ch
pex 8114 registers plx technology, inc. 298 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 note: although the pex 8114 supports only vc0, the vc1 posted credit fields are used for internal transactions, such as shadow writes. register 14-93. f70h pci-x interface itch vc&t threshold_1 bit(s) description type serial eeprom default 4:0 vc0 posted upper packet count vc0 posted upper pa cket beat limit. r/w yes 10h 7:5 not used r/w yes 000b 12:8 vc0 posted lower packet count vc0 posted lower packet beat limit. r/w yes 08h 15:13 not used r/w yes 000b 20:16 vc0 non-posted upper packet count vc0 non-posted upper packet be at limit. r/w yes 04h 23:21 not used r/w yes 000b 28:24 vc0 non-posted lower packet count vc0 non-posted lower packet beat limit. r/w yes 01h 31:29 not used r/w yes 000b register 14-94. f74h pci-x interface itch vc&t threshold_2 bit(s) description type serial eeprom default 4:0 vc0 completion upper packet count vc0 completion upper pa cket beat limit. r/w yes 10h 7:5 not used r/w yes 000b 12:8 vc0 completion lower packet count vc0 completion lower packet beat limit. r/w yes 08h 15:13 not used r/w yes 000b 20:16 vc1 posted upper packet count vc1 posted upper packet beat limit. th is information is listed for internal and serial eeprom config uration only ? not to be changed by users. r/w yes 04h 23:21 not used r/w yes 000b 28:24 vc1 posted lower packet count vc1 posted lower packet beat limit. this information is listed for internal and serial eeprom config uration only ? not to be changed by users. r/w yes 01h 31:29 not used r/w yes 000b
january, 2007 pci-x pl x-specific registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 299 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.14 pci-x plx-specific registers note: all errors in offset f80h generate msi/inta# interrupts, if enabled. table 14-22. pci-x plx-sp ecific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci-x interface device-speci fic error 32-bit error st atus (factory test only) f80h pci-x interface device-specific error 32-bit error mask (factory test only) f84h reserved pci-x interface completion buffer timeout f88h register 14-95. f80h pci-x interface device-specific error 32-bit error status (factory test only) bit(s) description type serial eeprom default 0 device-specific error completion fifo overflow status 0 = no overflow detected 1 = completion fifo overflow de tected when 4-deep completion fifo for ingress, or 2-deep comp letion fifo for egress, overflows r/w1cs yes 0 1 egress pram soft error overflow egress packet ram 1-bit soft error counter overflow. 0 = no error detected 1 = egress pram 1-bit soft error (8-bit counter) overflow when destination packet ram 1-bit soft e rror count is greater than or equal to 256, it generates an msi/ inta# interrupt, if enabled r/w1cs yes 0 2 egress llist soft error overflow egress link-list ram 1-bit soft error counter overflow. 0 = no error detected 1 = egress link-list 1-bit soft e rror (8-bit counter) overflow when destination module link lists ram 1- bit soft error count is greater than or equal to 256, it generates an msi/inta# interrupt, if enabled r/w1cs yes 0 3 egress pram ecc error egress packet ram 2-bit error detection. 0 = no error detected 1 = egress pram 2-bit ecc error detected r/w1cs yes 0 4 egress llist ecc error egress link-list ram 2-bit error detection. 0 = no error detected 1 = egress link-list 2-bit ecc error detected r/w1cs yes 0 5 ingress ram 1-bit ecc error source packet ram 1-bit soft error detection. 0 = no error detected 1 = ingress ram 1-bit ecc error detected r/w1cs yes 0 7:6 reserved 00b 8 ingress ram uncorrectable ecc error ingress packet ram 2- bit error detection. 0 = no 2-bit error detected 1 = packet ram uncorrectable ecc error detected r/w1cs yes 0 31:9 reserved 0-0h
pex 8114 registers plx technology, inc. 300 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-96. f84h pci-x interface device-specific error 32-bit error mask (factory test only) bit(s) description type serial eeprom default 0 device-specific error completion fifo overflow status mask 0 = when enabled, error ge nerates msi/inta# interrupt 1 = device-specific error comple tion fifo overflow status bit is masked/disabled r/ws yes 1 1 egress pram soft error overflow mask 0 = no effect on reporting activity 1 = egress pram soft error overflow bit is masked/disabled r/ws yes 1 2 egress llist soft error overflow mask 0 = no effect on reporting activity 1 = egress llist soft error overflow bit is masked/disabled r/ws yes 1 3 egress pram ecc error mask 0 = no effect on reporting activity 1 = egress pram ecc error bit is masked/disabled r/ws yes 1 4 egress llist ecc error mask 0 = no effect on reporting activity 1 = egress llist ecc error bit is masked/disabled r/ws yes 1 5 ingress ram 1-bit ecc error mask 0 = no effect on reporting activity 1 = ingress ram 1-bit ecc error bit is masked/disabled r/ws yes 1 7:6 reserved 00b 8 ingress ram uncorrectable ecc error mask 0 = no effect on reporting activity 1 = ingress ram uncorrectable ecc error bit is masked/disabled r/ws yes 1 31:9 reserved 0-0h register 14-97. f88h pci-x interface completion buffer timeout bit(s) description type serial eeprom default 7:0 target tag timeout r/w1c yes 00h 31:8 reserved 0000_00h
january, 2007 root port registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 301 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.15 root port registers table 14-23. root port register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 root control f8ch root status f90h root error command f94h root error status f98h error identification f9ch register 14-98. f8ch root control bit(s) description type serial eeprom default 0 system error on correctable error enable ro/fwd r/w/rev no ye s 0 0 1 system error on non-fatal error enable ro/fwd r/w/rev no ye s 0 0 2 system error on fatal error enable ro/fwd r/w/rev no ye s 0 0 3 pme interrupt enable ro/fwd r/w/rev no ye s 0 0 31:4 reserved 0000_000h register 14-99. f90h root status bit(s) description type serial eeprom default 15:0 pme requester id ro no 0000h 16 pme status r/w1c no 0 17 pme pending ro no 0 31:18 reserved 0000h register 14-100. f94h root error command bit(s) description type serial eeprom default 0 correctable error reporting enable ro/fwd r/w/rev no ye s 0 0 1 non-fatal error reporting enable ro/fwd r/w/rev no ye s 0 0 2 fatal error reporting enable ro/fwd r/w/rev no ye s 0 0 31:3 reserved 0-0h
pex 8114 registers plx technology, inc. 302 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-101. f98h root error status bit(s) description type serial eeprom default 0 correctable error received ro/fwd r/w1cs/rev no ye s 0 0 1 multiple correctable errors received ro/fwd r/w1cs/rev no ye s 0 0 2 uncorrectable error received ro/fwd r/w1cs/rev no ye s 0 0 3 multiple uncorrectable errors received ro/fwd r/w1cs/rev no ye s 0 0 4 first uncorrectable fatal ro/fwd r/w1cs/rev no ye s 0 5 non-fatal error message received ro/fwd r/w1cs/rev no ye s 0 6 fatal error message received ro/fwd r/w1cs/rev no ye s 0 26:7 reserved 0000_0h 31:27 advanced error interrupt message number ro no 00000b register 14-102. f9ch error identification bit(s) description type serial eeprom default 15:0 error correctable source identification ro/fwd ros/rev no no 0000h 0000h 31:16 error fatal/non-fatal source identification ro/fwd ros/rev no no 0000h 0000h
january, 2007 pci-x-specific registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 303 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.16 pci-x-specific registers table 14-24. pci-x-specific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci clock enable, strong or dering, read cycle value fa0h prefetch reserved fa4h
pex 8114 registers plx technology, inc. 304 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-103. fa0h pci clock enable, strong ordering, read cycle value bit(s) description type serial eeprom default 3:0 pci_clko_en[3:0] pci_clko_en[0]=1 enables pci_clko0 pci_clko_en[1]=1 enables pci_clko1 pci_clko_en[2]=1 enables pci_clko2 pci_clko_en[3]=1 enables pci_clko3 r/w yes 0h if strap_clk_mst=0 fh if strap_clk_mst=1 4 cache line prefetch line count controls the number of lines prefetched during memory reads. 0 = 1 cache line 1 = 2 cache lines; used only if the cache line size field (offset 0ch [7:0]) is less than or equal to 16 dwords (64 bytes) r/w yes 0 5 disable completion timeout timer refer to section 7.7, ?transacti on transfer failures.? r/w yes 0 6 enable long completion timeout timer refer to section 7.7, ?transacti on transfer failures.? r/w yes 1 7 disable bar0 r/w yes 0 8 force strong ordering after data is returned to the pex 8114 in response to a read request, the pex 8114 retries the same transaction until complete and does not attempt to gather data from other outstanding tr ansactions. r/w yes 0 9 reserved 0 10 pll lock control 0 resets on loss of pll lock, unless bits [11:10]=00b. (refer to table 14-25 for methods of handling loss of pll lock.) r/w yes 0 11 pll lock control 1 reset after timer timeout on loss of pll lock. (refer to table 14-25 for methods of handling loss of pll lock.) r/w yes 0 12 memory read line multiple enable r/w yes 0 13 address stepping enable r/w yes 0 14 sticky pci-x pll loss lock set when the pci-x pll loses pll lock. r/w1cs yes 0 15 sticky pci express pll loss lock set when the pci express pll loses pll lock. r/w1cs yes 0 26:16 maximum read cycle value r/w yes 7ffh 27 retry failure status r/w1c yes 0 31:28 reserved 0h
january, 2007 pci-x-specific registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 305 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 table 14-25. methods for handling loss of pll lock offset fa0h[11:10] description 00b default. ignores loss of pll lock. 01b a loss of pll lock immediat ely causes the pex 8114 to reset. 10b the pex 8114 attempts to tole rate loss of pll lock: when lock is re-acquired in less than 200 s, the pex 8114 does not reset when lock is not re-acquired wi thin 200 s, the pex 8114 is reset 11b the pex 8114 does not reset if loss of pll lock occurs. register 14-104. fa4h prefetch bit(s) description type serial eeprom default 7:0 reserved 00h 13:8 prefetch space count valid only in pci mode. not used in pci-x mode. specifies the number of dwords to pr efetch for memory reads originating on the pci bus that are forwarded to the pci express interface. only even values between 0 and 32 are allowed. when the pex 8114 is configured as a forward bridge, prefetching occurs for all memory reads of prefetchable and non-prefetchable memory space. this occurs because the bars are not used for memory reads, making it impossible to determine whether the space is prefetchable. in reverse transparent bridge mode, prefetching occurs only for memory reads that address prefetchable memory space. prefetching is quad-word aligned, in that data is prefetched to the end of a quad-word boundary. the number of dwords prefetched is as follows: pex 8114 prefetches 2 dwords when the following conditions are met: ? prefetch space count field is cleared to 00h, and ? pci_ad0 or pci_ad1 is high ? pci_req64# is asserted (low) pex 8114 prefetches 1 dword when the following conditions are met: ? prefetch space count field is cleared to 00h, and ? pci_ad0 or pci_ad1 is high ? pci_req64# is de-asserted (high) when the prefetch space count field contains an even value greater than 0 and pci_ad2 is high, the number of prefetched dwords is 1 dword less than the value in the prefetch space count field; otherwise, the number of dwords pr efetched is equal to the value in the prefetch space count field. only even values between 0 and 32 are allowed. odd values provide unexpected results. r/w yes 20h 31:14 reserved 0-0h
pex 8114 registers plx technology, inc. 306 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.17 pci arbiter registers table 14-26. pci arbiter register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 arbiter 0 fa8h arbiter 1 fach arbiter 2 fb0h register 14-105. fa8h arbiter 0 bit(s) description type serial eeprom default 2:0 arbiter allocation 0 r/w yes 000b 7:3 reserved 00000b 10:8 arbiter allocation 1 r/w yes 001b 15:11 reserved 00000b 18:16 arbiter allocation 2 r/w yes 010b 23:19 reserved 00000b 26:24 arbiter allocation 3 r/w yes 011b 31:27 reserved 00000b register 14-106. fach arbiter 1 bit(s) description type serial eeprom default 2:0 arbiter allocation 4 r/w yes 100b 7:3 reserved 00000b 10:8 arbiter allocation 5 r/w yes 000b 15:11 reserved 00000b 18:16 arbiter allocation 6 r/w yes 001b 23:19 reserved 00000b 26:24 arbiter allocation 7 r/w yes 010b 31:27 reserved 00000b register 14-107. fb0h arbiter 2 bit(s) description type serial eeprom default 2:0 arbiter allocation 8 r/w yes 011b 7:3 reserved 00000b 10:8 arbiter allocation 9 r/w yes 100b 23:11 reserved 0-0h 24 grant mode r/w yes 0 31:25 reserved 0000_000b
january, 2007 advanc ed error reporting capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 307 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 14.18 advanced error reporting capability registers table 14-27. advanced error reporting capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset capability ve r s i o n ( 1h ) pci express extended capability id ( 0001h )fb4h uncorrectable error status fb8h uncorrectable error mask fbch uncorrectable error severity fc0h correctable error status fc4h correctable error mask fc8h advanced error capa bilities and control fcch header log_0 fd0h header log_1 fd4h header log_2 fd8h header log_3 fdch secondary uncorrect able error status fe0h secondary uncorrectable error mask fe4h secondary uncorrectable error severity fe8h secondary uncorrectable error pointer fech secondary header log ff0h ? ffch
pex 8114 registers plx technology, inc. 308 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-108. fb4h pci express enhanced capability header bit(s) description type serial eeprom default 15:0 pci express extended capability id ro yes 0001h 19:16 capability version ro yes 1h 31:20 next capability offset ro yes 138h register 14-109. fb8h uncorrectable error status bit(s) description type serial eeprom default 0 training error status 0 = no error detected 1 = error detected r/w1cs yes 0 3:1 reserved 000b 4 data link protocol error status 0 = no error detected 1 = error detected r/w1cs yes 0 11:5 reserved 0000_000b 12 poisoned tlp status 0 = no error detected 1 = error detected r/w1cs yes 0 13 flow control protocol error status 0 = no error detected 1 = error detected r/w1cs yes 0 14 completion timeout status 0 = no error detected 1 = error detected r/w1cs yes 0 15 completer abort status 0 = no error detected 1 = error detected r/w1cs yes 0 16 unexpected completion status 0 = no error detected 1 = error detected r/w1cs yes 0 17 receiver overflow status 0 = no error detected 1 = error detected r/w1cs yes 0 18 malformed tlp status 0 = no error detected 1 = error detected r/w1cs yes 0 19 ecrc error status 0 = no error detected 1 = error detected r/w1cs yes 0 20 unsupported request error status 0 = no error detected 1 = error detected r/w1cs yes 0 31:21 reserved 0-0h
january, 2007 advanc ed error reporting capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 309 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-110. fbch uncorrectable error mask bit(s) description type serial eeprom default 0 training error mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 3:1 reserved 000b 4 data link protocol error mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 11:5 reserved 0000_000b 12 poisoned tlp mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 13 flow control protocol mask 0 = no mask is set 1 = error reporting, first error update, and header logging are masked for this error r/ws yes 0 14 completion timeout mask 0 = no mask is set 1 = error reporting, first error update, and header logging are masked for this error r/ws yes 0 15 completer abort mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 16 unexpected completion mask 0 = no mask is set 1 = error reporting, first error update, and header logging are masked for this error r/ws yes 0 17 receiver overflow mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 18 malformed tlp mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 19 ecrc error mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 20 unsupported request error mask 0 = no mask is set 1 = error reporting, first error update , and header logging are masked for this error r/ws yes 0 31:21 reserved 0-0h
pex 8114 registers plx technology, inc. 310 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-111. fc0h uncorrectable error severity bit(s) description type serial eeprom default 0 training error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 3:1 reserved 000b 4 data link protocol error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 11:5 reserved 0000_000b 12 poisoned tlp severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 13 flow control protocol error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 14 completion timeout severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 15 completer abort severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 16 unexpected completion severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 17 receiver overflow severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 18 malformed tlp severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 19 ecrc error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 20 unsupported request error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 31:21 reserved 0-0h
january, 2007 advanc ed error reporting capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 311 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-112. fc4h correctable error status bit(s) description type serial eeprom default 0 receive error status 0 = no error detected 1 = error detected r/w1cs yes 0 5:1 reserved 0-0h 6 bad tlp status 0 = no error detected 1 = error detected r/w1cs yes 0 7 bad dllp status 0 = no error detected 1 = error detected r/w1cs yes 0 8 replay number rollover status 0 = no error detected 1 = error detected r/w1cs yes 0 11:9 reserved 000b 12 replay timer timeout status 0 = no error detected 1 = error detected r/w1cs yes 0 31:13 reserved 0-0h register 14-113. fc8h correctable error mask bit(s) description type serial eeprom default 0 receive error mask 0 = error reporting not masked 1 = error reporting masked r/ws yes 0 5:1 reserved 0-0h 6 bad tlp mask 0 = error reporting not masked 1 = error reporting masked r/ws yes 0 7 bad dllp mask 0 = error reporting not masked 1 = error reporting masked r/ws yes 0 8 replay number rollover mask 0 = error reporting not masked 1 = error reporting masked r/ws yes 0 11:9 reserved 000b 12 replay timer timeout mask 0 = error reporting not masked 1 = error reporting masked r/ws yes 0 31:13 reserved 0-0h
pex 8114 registers plx technology, inc. 312 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-114. fcch advanced error capabilities and control bit(s) description type serial eeprom default 4:0 first error pointer identifies the bit position of the first error reported in the uncorrectable error status register. ros yes 1_1111b 5 ecrc generation capable 0 = ecrc generation not supported 1 = ecrc generation supported, but must be enabled ro yes 1 6 ecrc generation enable 0 = ecrc generation disabled 1 = ecrc generation enabled r/ws yes 0 7 ecrc checking capable 0 = ecrc checking not supported 1 = ecrc checking supported, but must be enabled ro yes 1 8 ecrc checking enable 0 = ecrc checking disabled 1 = ecrc checking enabled r/ws yes 0 31:9 reserved 0-0h register 14-115. fd0h header log_0 bit(s) description type serial eeprom default 31:0 tlp header_0 first dword header. tlp header associated with error. ros yes 0-0h register 14-116. fd4h header log_1 bit(s) description type serial eeprom default 31:0 tlp header_1 second dword header. tlp header associated with error. ros yes 0-0h register 14-117. fd8h header log_2 bit(s) description type serial eeprom default 31:0 tlp header_2 third dword header. tlp header associated with error. ros yes 0-0h register 14-118. fdch header log_3 bit(s) description type serial eeprom default 31:0 tlp header_3 fourth dword header. tlp header associated with error. ros yes 0-0h
january, 2007 advanc ed error reporting capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 313 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-119. fe0h secondary uncorrectable error status bit(s) description type serial eeprom default 0 target abort on split completion status 0 = no error detected 1 = error detected r/w1cs yes 0 1 master abort on split completion status 0 = no error detected 1 = error detected r/w1cs yes 0 2 received target abort status 0 = no error detected 1 = error detected r/w1cs yes 0 3 received master abort status 0 = no error detected 1 = error detected r/w1cs yes 0 4 reserved 0 5 unexpected split completion error status 0 = no error detected 1 = error detected r/w1cs yes 0 6 uncorrectable split completion message data error status 0 = no error detected 1 = error detected r/w1cs yes 0 7 uncorrectable data parity error detected status 0 = no error detected 1 = error detected r/w1cs yes 0 8 uncorrectable attribute parity error detected status 0 = no error detected 1 = error detected r/w1cs yes 0 9 uncorrectable address parity error detected status 0 = no error detected 1 = error detected r/w1cs yes 0 10 delayed transaction discard timer expired status 0 = no error detected 1 = error detected r/w1cs yes 0 11 perr# assertion detected 0 = no error detected 1 = error detected r/w1cs yes 0 12 serr# assertion detected 0 = no error detected 1 = error detected r/w1cs yes 0 13 internal bridge error status 0 = no error detected 1 = error detected r/w1cs yes 0 31:14 reserved 0-0h
pex 8114 registers plx technology, inc. 314 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-120. fe4h secondary uncorrectable error mask bit(s) description type serial eeprom default 0 target abort on split completion mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 0 1 master abort on sp lit completion mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 0 2 received target abort mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 0 3 received master abort mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 1 4 reserved 0 5 unexpected split completion error mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 1 6 uncorrectable split completi on message data error mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 0 7 uncorrectable data parity error detected mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 1
january, 2007 advanc ed error reporting capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 315 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 8 uncorrectable attribute parity error detected mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 1 9 uncorrectable address parity error detected mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 1 10 delayed transaction discard timer expired mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 1 11 perr# assertion detected mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 0 12 serr# assertion detected mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 1 13 internal bridge error mask 0 = no mask is set 1 = error reporting, first error updat e, and header logging are masked for this error r/ws yes 0 31:14 reserved 0-0h register 14-120. fe4h secondary uncorrectable error mask (cont.) bit(s) description type serial eeprom default
pex 8114 registers plx technology, inc. 316 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-121. fe8h secondary uncorrectable error severity bit(s) description type serial eeprom default 0 target abort on split completion severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 1 master abort on spli t completion severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 2 received target abort severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 3 received master abort severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 4 reserved 0 5 unexpected split completion error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 6 uncorrectable split completion message data error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 7 uncorrectable data parity error detected severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 8 uncorrectable attribute parity error detected severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 9 uncorrectable address parity error detected severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 10 delayed transaction discard timer expired severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 11 perr# assertion detected severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 12 serr# assertion detected severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 1 13 internal bridge error severity 0 = error reported as non-fatal 1 = error reported as fatal r/ws yes 0 31:14 reserved 0-0h
january, 2007 advanc ed error reporting capability registers expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 317 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 register 14-122. fech secondary uncorrectable error pointer bit(s) description type serial eeprom default 4:0 secondary uncorrectable error pointer ros no 00000b 31:5 reserved 0000_000h register 14-123. ff0h ? ffch secondary header log bit(s) description type serial eeprom default 35:0 transaction attribute ros no 0-0h 39:36 transaction command lower ros no 0-0h 43:40 transaction command upper ros no 0-0h 63:44 reserved 0-0h 127:64 transaction address ros no 0-0h
pex 8114 registers plx technology, inc. 318 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 319 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 15 test and debug 15.1 physical layer loop-back operation 15.1.1 overview physical layer loop-back functions are used to test serdes in the pex 8114 , connections between devices, serdes of external devices, and certain pex 8114 and external digital logic. the pex 8114 supports five types of loop-back operations: internal loop-back ? connects serdes serial tx output to serial rx input. the prbs generator is used to create a pseudo-random data pattern that is transmitted and returned to the prbs checker. analog loop-back master ? this serdes test depends on an external device or dumb connection ( such as a cable) to loop back the transmitted data to the pex 8114. if an external device is used, it must not include its elastic buffer in the lo op-back data path because no skip ordered-se t s are transmitted. use the prbs generator and ch ecker to create and check the data pattern. digital loop-back master ? as with the analog loop-back master mode, this method depends upon an external device to loop back the transmitted data. this method is best utilized with an external device that includes at least its elasti c buffer in the loop-back data path. the pex 8114 provides user-definable data pattern generators and checkers that insert the skip ordered-se t at the proper intervals. analog loop-back slave ?the pex 8114 enters analog loop-back slave mode when an external device transmits training sets with the physical layer port command register port 0 loop-back bit (offset 230h [0]) set, and the physical layer test register analog loop-back enable bit (offset 228h [4]) is set. the received data is looped back from the serdes 10-bit receive interface to the 10-bit transmit interface. all digital logic is exclud ed from the loop-back data path. digital loop-back slave ? the pex 8114 enters digital loop-back slave mode when an external device transmits training sets with the physical layer port command register port 0 loop-back bit set, and the analog loop-back enable bit is clear. in this mode, the data is looped back at an 8-bit level, which includes the pex 8114 elastic buff er, 8b/10b decoder, and 8b/10b encoder in the loop-back data path.
test and debug plx technology, inc. 320 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.1.2 loop-back test modes the pex 8114 supports all loop-back modes described in the pci express base 1.0a . to establish the pex 8114 as a loop-back master, the serial eeprom is used to write 1 to the physical layer port command register port 0 ready as loop-back master bit (offset 230h [3]). this enables the pex 8114 to set its port 0 loop-back bit (offset 230h [0]) in the training sets during the configuration.linkwidth.start state. after the pex 8114 is established as a loop-back master, the physical layer port command register port 0 ready as loop-back master bit is set. depending on the capability of the loop-back slave, the prbs generator or bit-pattern generator is used to cr eate a bit stream that is checked by checking logic. when the pex 8114 is established as a loop-back sl ave, it can operate as an analog or digital (default) far-end device. analog loop-back mode is selected by setting the physical layer test register analog loop- back enable bit (offset 228h [4]) to 1. in analog loop-back mode, the received data is looped back from the 10-bit received data, to the 10-bit transmit data. when digital loop-back mo de is selected (power-on default), the data is looped back from the 8-bit decoded received data to the 8-bit transmit da ta path. this loop-back point allows the elastic buffer 8b/10b decoder, and 8b/10b encoder to be included in the test data path. digital loop-back mode requires that skip ordered-se t s are included in the data stream. 15.1.2.1 internal loop-back figure 15-1 illustrates the loop-b ack data path when internal loop- back mode is enabled. the only items in the data path are the serializer and de-s erializer. loop-back mode is used when the serdes built-in self-test (bist) is enabled. serdes bist is intended to overlap with the serial eeprom load operation. to achieve this overlap, the physical layer test register serdes bist enable bit (offset 228h [7]) is written early in the serial eeprom load operation. after the serdes bist enable bit is set, serdes is placed in loop-back mode and the prbs generator is started. the bist is run fo r 512 s; if an error is detected on a serdes, then the quad serdes[0-3] diagnostics data register (offset 238h ) logs the number of prbs errors generated for the group of serdes lanes. while the se rdes bist is in progress, the prbs test data is present on the external txp and txn balls. the tx pad txn signals must have an ac-coupled, 50-ohm termination to ground. the reloading of the seri al eeprom register load has no effect on the serdes bist. figure 15-1. internal loop-back (analog near end) data path prbs gen prbs chk tx pad rx pad pex 8114
january, 2007 loop-back test modes expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 321 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.1.2.2 analog loop-back master analog loop-back mode is normally used for analog far-end testing; however, the mode can also be used to re-create the previously described bist by looping back the data with a cable. (refer to figure 15-2 .) looping back with a cable includes the internal b ond, external balls, any board trace, and connectors in the test data path. (refer to figure 15-3 .) to cause the pex 8114 to request to become a lo op-back master, the following must be accomplished: 1. after the link is up, a configuration write to the physical layer port command register port 0 loop-back bit (offset 230h [1]) causes the pex 8114 to transiti on from the l0 state to recovery, then to the loop-back state: ? if a cable is used for a loop -back, the pex 8114 transitions from the configuration state to the loop-back state. connect this cable only after the upstream link is up and configuration writes are possible. ? if the cable is connected before the upstream device is able to set the analog loop-back enable bit, the link with the cable can reach the l0 state and not go to the loop-back state. ? cable length is limited only by the pc i express drivers an d cable properties. 2. after the pex 8114 is in the loop-back state, the physical layer port command register port 0 ready as loop-back master bit is set: ? at this time, the prbs engine is enabled by setting the prbs enable bit (offset 228h [16]). ? the returned prbs data is checked by the prbs checker. errors are logged in the quad serdes[0-3] diagnostics data register (offset 238h ). figure 15-2. analog far-end loop-back figure 15-3. cable loop-back prbs gen prbs chk tx pad rx pad pci-e loop-back slave device tx pad rx pad pci-e = pci express pex 8114 prbs gen prbs chk tx pad rx pad pex 8114
test and debug plx technology, inc. 322 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.1.2.3 digital loop-back master the only difference between the analog and digita l loop-back master modes is that the external device is assumed to possess certain digital logic in the loop-back data path. because this includes the elastic buffer, skip ordered-se t s must be included in the test data pattern. for the pex 8114, this precludes prbs engine use. the pex 8114 provides the user data patterns (offsets 210h through 21ch ) transmitter for digital far-end loop-back test ing. the following mu st be accomplished: 1. after loop-back master mode is established, configuration writes are used to fill the test data pattern registers. the physical layer test register test pattern enable bit (offset 228h [28]) is set; this starts the transmission of the user data pattern on all lanes: ? if the physical layer test register port/serdes test pattern enable select bit (offset 228h [5]) is also set, the test pattern is transmitted on all lanes, regardless of width. ? if the port/serdes test pattern enable select bit is clear, then the test pattern is transmitted only on the lanes. 2. skip ordered-se t s are inserted at the interval determined by the value in the skip interval register (default value is 1,180 symbol times) at the nearest data pattern boundary. the test pattern checker ignores skip ordered-se t s returned by the loop-back slave, because the number of skip symbols received are different from the number transmitted. 3. all other data is compared to the data transmitted and errors are logged in the quad serdes[0-3] diagnostics data register. figure 15-4. digital far-end loop-back utp tx utp chk tx pad rx pad pci-e loop-back slave device tx pad rx pad ebuffer pex 8114
january, 2007 loop-back test modes expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 323 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.1.2.4 analog loop-back slave the pex 8114 becomes an analog loop-back sl ave if it receives training sets with the physical layer port command register port 0 loop-back bit (offset 230h [0]) set while the physical layer test register analog loop-back enable bit (offset 228h [4]) is set. (refer to figure 15-5 .) while an analog loop-back slave, the pex 8114 only includes the de-s erializer and serializer in the loop-back data path. the loop-back master must provide the test data pattern and data pattern checking. it is unnecessary for the loop- back master to include skip ordered-se t s in the data pattern. figure 15-5. analog loop-back slave mode 15.1.2.5 digital loop-back slave the pex 8114 becomes a digital lo op-back slave if it receives training sets with the physical layer port command register port 0 loop-back bit set while the physical layer test register analog loop- back enable bit is clear. (refer to figure 15-6 .) when the pex 8114 is a digital loop -back slave, it includes the elas tic buffer and 8b/10b decoder and encoder in the loop-back data path. the loop-back ma ster must provide the test data pattern and data pattern checker. additionally, the master must transmit valid 8b/10b symbols, for the loop-back data from the slave to be valid. the loop-back master must al so transmit skip ordered-se t s with the data pattern. the data checker must make provisions for the pex 8114 to return more or fewer skip symbols than it received. figure 15-6. digital loop-back slave mode data gen data chk tx pad rx pad pci-e loop-back master device tx pad rx pad pex 8114 data tx data chk tx pad rx pad pci-e loop-back master device tx pad rx pad ebuffer 8b/10b dec 8b/10b enc pex 8114
test and debug plx technology, inc. 324 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.2 pseudo-random and bit-pattern generation the serdes quad contains a prbs generator and checker. the prbs generator is based on a 7-bit linear feedback shift register (l fsr), which can generate up to (2 7 ? 1) unique patterns. the prbs logic is assigned to a serdes within the quad by manipulating the physical layer test register prbs association field (offset 228h [9:8]). the prbs bit stream is us ed for internal serdes or analog far-end loop-back testing. the pex 8114 also provides a method of creating a repeating user-defined bit pattern. each of the four 32-bit test pattern registers are loaded with a 32-bit data pattern. after the pex 8114 is established as a loop-back master, the physical layer test register test pattern enable bit (offset 228h [28]) is set to 1. the pex 8114 proceeds to transmit the data patt ern on all lanes, starting with byte 0 of the test pattern_0 register, and continuing in sequence through the byte 3 of the test pattern_ 3 register. skip ordered-se t s are inserted at the proper intervals, which makes this method appropriate for digital far-end loop-back testing. the received pattern is checked/compa red for errors. the errors are logged and retrieved by reading the quad serdes[0-3] diagnostics data register.
january, 2007 jtag interface expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 325 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.3 jtag interface the pex 8114 provides a jtag bounda ry scan interface, which is util ized to debug board connectivity for each ball. 15.3.1 ieee 1149.1 and 1149.6 test access port the ieee 1149.1 test access port (tap), commonly referred to as the jtag (joint test action group) debug port , is an architectural standard described in the ieee standard 1149.1-1990 . the ieee standard 1149.6-2003 defines extensions to 1149.1 to support pci express serdes testing. these standards describe methods for accessing internal bridge facilities, using a four- or five-signal interface. the jtag debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. thes e enhancements, which comply with ieee standard 1149.1b-1994 specifications for vendor-specific extensions , are compatible with sta ndard jtag hardware for boundary-scan system testing. jtag signals ? jtag debug port implements the four required jtag signals ? jtag_tck , jtag_tdi , jtag_tdo , jtag_tms ? and optional jtag_trst# signal clock requirements ? the jtag_tck signal frequency ranges from dc to 10 mhz jtag reset requirements ? refer to section 15.3.4, ?jtag reset input trst#?
test and debug plx technology, inc. 326 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.3.2 jtag instructions the jtag debug port provides the ieee standard 1149.1-1990 extest, sample/preload, bypass, and idcode instructions. ieee standard 1149.6-2003 extest_pulse and extest_train instructions are also supported. private instructions are for plx use only. invalid instructions behave as bypass instructions. table 15-1 defines the jtag instructions, along with their input codes. the pex 8114 returns the idcode values listed in table 15-2 . table 15-1. jtag instructions instruction input code comments extest 00000b ieee standard 1149.1-1990 idcode 00001b sample/preload 00010b bypass 11111b extest_pulse 00011b ieee standard 1149.6-2003 extest_train 00100b private a a. warning: non-plx use of private instructions can ca use a component to operate in a hazardous manner. table 15-2. pex 8114 jtag idcode values unit of measure version part number plx manufacturer identity least significant bit bits 1000b 0001_1111_1011_0010b 001_1100_1101b 1 hex 8h 1fb2h 1cdh 1h decimal 8 8114 461 1
january, 2007 jtag boundary scan expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 327 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 15.3.3 jtag boundary scan scan description language (bsdl), ieee 1149.1b-1994 , is a supplement to ieee standard 1149.1- 1990 and ieee 1149.1a-1993, ieee standard test access port and boundary-scan architecture. bsdl, a subset of the ieee 1076-1993 st andard vhsic hardware de scription language (vhdl) , defines a rigorous description of testability features in components which comply with the standard . it is used by automated test pattern generation tools for package interconnect tests and electronic design automation (eda) tools for synthesized test logic and verification. bsdl supports robust extensions used for internal test generation and to write software for hardware debug and diagnostics. the primary components of bsdl include the logical port description, physical ball map, instruction set, and boundary register description. the logical port description assigns symbolic names to the pex 8114 balls. each ball includes a logical type of in , out , in out , buffer , or linkage that defines the logical direction of signal flow. the physical ball map correlates the pex 8114 logical ports to the physical balls of a specific package. a bsdl description can have several physical ball maps; each map is given a unique name. instruction set statements describe the bit patterns that must be shifted into the instruction register to place the pex 8114 in the various test modes defined by the standard . instruction set statements also support descriptions of instructions that are unique to the pex 8114. the boundary register description lists each cell or sh ift stage of the boundary register. each cell has a unique number; the cell numbered 0 is the closest to the test data out (tdo) ball and the cell with the highest number is closest to the test data in (tdi) ball. each cell contains fu rther details, including: cell type logical port associated with the cell logical function of the cell safe value control cell number disable value result value 15.3.4 jtag reset input trst# the jtag_trst# input ball is the asynchronous jtag logic reset. when jtag_trst# is asserted, it causes the pex 8114 jtag tap controller to initialize. in addition, when the jtag tap controller is initialized, it selects the pex 8114 normal logic path (core-to-i/o). it is recommended that the following be taken into consideration when implementing the asynchronous jtag logic reset on a board: when jtag functionality is required, consider one of the following: ? jtag_trst# input signal to use a low-to-high transition once during the pex 8114 boot-up, along with the system pex_perst# signal ? hold the pex 8114 tms ball high while transitioning the pex 8114 jtag_tck ball five times when jtag functionality is not required, dir ectly connect the jtag_trst# signal to ground
test and debug plx technology, inc. 328 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 this page intentionally left blank.
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 329 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 16 electrical specifications 16.1 introduction this chapter contains the pex 8114 power-on sequencing rules and electrical specifications. 16.2 pex 8114 power-on sequence the pex 8114 requires three voltage sources: 3.3v for i/o power and clock pll power, supplied by the vdd33 and vdd33a balls 1.35 to 1.8v for serdes transmitter common-mode biasing, supplied by the vtt_pex[1:0] balls 1.0v 0.1v for serdes/core power, supplied by the vdd10 , vdd10a , and vdd10s balls vdd10, vdd10a, and vdd10s must power-up first and power-down last. if properly sequenced, all supply rails power-up within 50 ms of one another. 16.3 absolute maximum ratings maximum limits indicate the temper atures and voltages above which permanent damage can occur. proper operation at these conditions is not guaranteed, and continuous operation of the pex 8114 at these limits is not recommended. table 16-1. absolute maximum rating (all voltages referenced to vss system ground) item symbol absolute maximum rating units i/o interface supply voltage vdd33 -0.5 to +4.6 v pll supply voltage vdd33a -0.5 to +4.6 v serdes analog supply voltage vdd10a -0.3 to +1.65 a a. the serdes analog and digital power supplies must track within 0.01v of one another. v serdes digital supply voltage vdd10s -0.3 to +1.65 a v serdes termination supply voltage vtt_pex[1:0] 2.5 v core (logic) supply voltage vdd10 -0.3 to +1.65 v input voltage (3.3v interface) v i -0.3 to +4.6 v core vdd voltage vdd10 1.0 0.1 v operating ambient temperature t a -40 to +85 c storage temperature t stg -55 to +150 c
electrical specifications plx technology, inc. 330 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 table 16-2. capacitance for logic/control i/o item symbol conditions min typ max unit input ball c in vdd33/a = 0.0v, vdd10/a/s = 0.0v 46pf output ball c out 610pf input/output and three-state ball c i/o 610pf table 16-3. power dissipation parameter symbol conditions a a. pex_refclkn/p = 100 mhz. a 250-mhz clock is synthesized from pex_refclkn/p and used internally to clock the serdes and core logic. min. typ max unit power dissipation pd vdd33/a = 3.3v, 10% vdd10/a/s = 1.0v, 10% vtt_pex[1:0] = 1.5v, 10% 300 1.475 115 375 1.93 150 mw w mw
january, 2007 digital logic interface operating characteristics expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 331 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 16.4 digital logic interface operating characteristics unless specified otherwise, ge neral operating conditions are: vdd33 = 3.3v 0.3v, vdd10 = 1.0v 0.1v, t a = -40 to +85c table 16-4. digital logic interface operating electrical characteristics symbol parameter test conditions ranges and limits units min typ max vdd33 operating voltage (i/o) 3.0 3.3 3.6 v vdd33a operating voltage for pll 3.0 3.3 3.6 v vdd10 operating voltage (core) 0.9 1.0 1.1 v vtt_pex serdes termination supply voltage 1.35 1.5 1.8 v v il input low voltage for pci/pci-x inputs -0.5 0.3 vdd33 v input low voltage for ttl inputs a a. cmos technology designed as ttl-compatible. 0.8 v v ih input high voltage for pci/pci-x inputs 0.5 vdd33 vdd33 +0.5 v input high voltage for ttl inputs a 2.0 v i in input leakage current 0v < v in < vdd33 i/o balls set to high impedance -10.0 b +10.0 b b. current into the ball is shown as ?+? and current out of the ball is shown as ?-?. a v ol output low voltage pci/pci-x outputs i load = 1500 a 0.1 vdd33 v output low voltage ttl outputs a i load = 8 ma c c. exception ? i load = +12 ma for ee_do ball. 0.4 v v oh output high voltage pci/pci-x outputs i load = -500 a 0.9 vdd33 v output high voltage ttl outputs a i load = -8 ma d d. exception ? i load = -12 ma for ee_do ball. 2.4 v
electrical specifications plx technology, inc. 332 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 16.4.1 serdes/lane interface dc characteristics unless specified otherwise, ge neral operating conditions are: vdd33a = 3.3v 0.3v, vdd10s = vdd10a = 1.0v 0.1v, t a = -40 to +85c table 16-5. serdes interface dc electrical characteristics symbol parameter test conditions min typ max units vtt_pex[1:0] serdes termin ation voltage 1.35 1.5 165 v vdd10a serdes analog supply voltage a 0.9 1.0 1.1 v vdd10s serdes digital supply voltage a 0.9 1.0 1.1 v i dda serdes supply current pex_re fclkn/p = 100 mhz 65 97.5 ma i dds serdes supply current pex_refclkn/p = 100 mhz 140 210 ma i vtt_pex serdes termination supply current 87 105 ma pex_pet transmit outputs v tx-diffp-p differential peak-to-peak output voltage 1.3v < v tt < 1.6v b 0.8 1.0 1.2 v v tx-cm ac_p rms a peak output voltage 20 mv v tx-cm-dc- active-idle-delta absolute delta between dc common-mode during l0 and electrical idle 0.0 100 mv v tx-cm-dc- line-delta maximum common mode voltage delta between pex_petn[3:0] and pex_petp[3:0] 25 mv v tx-de-ratio de-emphasis diff erential output voltage ratio 0.0 c -3.5 -7.96 c db v tx-idle_diff_ps maximum peak output voltage during link idle state 20 mv v tx-rcv-detect amount of common-mode voltage change allowed during receiver detection 600 mv i tx-short output short-circuit current v tx-out = 0.0v 90 ma z tx-diff-dc differential output impedance 80 100 120 ohm z tx-dc output impedance for each transmitter in all power states 40 ohm rl tx-diff differential return loss 12 db rl tx-cm common-mode return loss 6 db
january, 2007 serdes/lane interface dc characteristics expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 333 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 pex_pern[3:0]/pex_perp[3: 0] receiver inputs v rx-diffp-p differential peak-to-peak input voltage 0.175 1.200 v v rx-idle-det- diffp-p idle detect threshold voltage 65 175 mv v rx-cm ac receiver common-mode voltage for ac coupling 150 mv z rx-diff-dc dc differential input impedance 80 100 120 ohm z rx-dc dc input impedance 40 50 60 ohm z rx-high-imp-dc input impedance during power down conditions 200k ohm rl rx-diff differential return loss 15 db rl rx-cm common-mode return loss 6 db a. the serdes analog and digital power supplies must track within 0.01v of one another. b. for v tt voltages between 1.0 to 1.8v, refer to table 16-1 . [the v tt test condition for v tx-diffp-p (listed above) is derived from table 16-1 .] c. v tx-de-ratio can be programmed to exceed the pci ex press r1.0a of min -3.0, max -4.0. table 16-5. serdes interface dc electrical characteristics (cont.) symbol parameter test conditions min typ max units
electrical specifications plx technology, inc. 334 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 16.5 serdes interface ac specifications unless specified otherwise, ge neral operating conditions are: vdd33a = 3.3v 0.3v, vdd10s = vdd10a = 1.0v 0.1v, t a = -40 to +85c table 16-6. serdes interface ac electrical characteristics symbol parameter test conditions min typ max units pex_pet transmit outputs ui unit interval 399.88 400 400.12 ps t tx-rise differential signal rise time 20 to 80% 0.125 0.3 ui t tx-fall differential signal fall time 20 to 80% 0.125 0.3 ui t tx-idle-min minimum idle time for transmitter 50 ui t tx-idle-to- diff-data transmitter recovery time from idle state to fully active transmit state 20 ui t tx-eye transmitter eye width 0.7 ui l tx-skew lane-to-lane static output skew for all lanes in port/link 1.3 ns pex_per receive inputs ui unit interval 399.88 400 400.12 ps t rx-idle-det- diff-entertime maximum time required for receiver to recognize and signal an unexpected idle on link 10 ms t rx-eye receiver eye width 0.4 ui t rx-skew total skew 20 ns table 16-7. pex_refclock ac specifications symbol parameter test conditions min typ max units pex_refclk 100 mhz differential reference clock input 100 mhz v cm input common mode voltage 0.6 0.65 0.7 v clkin dc input clock duty cycle 40 50 60 % t r /t f input clock rise/fall times 1.5 ns v sw differential input voltage swing a a. ac coupling required. 0.25 1.6 v r term reference clock differential termination 110 ohm
january, 2007 serdes interface ac specifications expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 335 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 table 16-8. pci 33-mhz ac specifications symbol parameter test conditions min typ max units notes t cyc pci clk cycle time 30 ? ns t val clk to signal valid delay ? bused signals 211ns 1 , 2 , 3 , 8 t val (ptp) clk to signal valid delay ? point-to-point signals 212ns 1 , 2 , 3 , 8 t on float to active delay 2 ns 1 , 8 , 9 t off active to float delay 28 ns 1 , 9 t su input setup time to clk ? bused signals 7ns 3 , 4 , 10 t su (ptp) input setup time to clk ? point-to-point signals 10, 12 ns 3 , 4 t h input hold time from clk 0 ns 4 t rst reset active time after power stable 1ms 5 t rst-clk reset active time after clk stable 100 s 5 t rst-off reset active to output float delay 40 ns 5 , 6 t rrsu pci_req64# to pci_rst# setup time 10t cyc ns t rrh pci_rst# to pci_req64# hold time 050ns t rhfa pci_rst# high to first configuration access 2 25 clocks t rhff pci_rst# high to first pci_frame# assertion 5clocks t ckskew clock skew between any pci_clko[3:0] outputs 130 ps notes: 1. refer to the timing measurement conditions in the pci r3.0, figure 7-3. it is important that all driv en signal transitions drive to their v oh or v ol level within one t cyc . 2. minimum times are measured at the package ball with the load circuit illustrated in the pci r3.0, figure 7-7. maximum times are measured with the load circuit ill ustrated in the pci r3.0, figures 7-5 and 7-6. 3. pci_gnt# and pci_req# are point-to-point signals and have differ ent input setup time s than bused signals. the setup for pci_gnt# and pci_req# at 66 mh z is 5 ns. all othe r signals are bused. 4. refer to the timing measurement condi tions in the pci r3.0, figure 7-4. 5. when pci_m66en is asserted, clk is stable when it meets the requirements in the pci r3.0, section 7.6.4.1. pci_rst# is asserted and de-asserted asynchronously with respect to clk. (refer to the pci r3.0, secti on 4.3.2, for further details.) 6. float all output drivers when pci_rst# is active. (refer to the pci r3.0, section 4.3.2, for further details.) 8. when pci_m66en is asserted, the minimum specification for t val (min), t val (ptp)(min), and t on can be reduced to 1 ns if a mechanism is provided to guarantee a minimu m value of 2 ns when pci_m66en is de-asserted. 9. for purposes of active/fl oat timing measurements, th e hi-z or ?off? state is defined as when the total current delivered through the component ball is less than or e qual to the leakage current specification. 10. setup time applies when the pex 8114 is not driving the ball. devices cannot concurrently drive and receive signals. (refer to the pci r3.0, section 3. 10, item 9, for further details.)
electrical specifications plx technology, inc. 336 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 table 16-9. pci 66-mhz ac specifications symbol parameter test conditions min typ max units notes t cyc pci clk cycle time 15 30 ns t val clk to signal valid delay ? bused signals 26ns 1 , 2 , 3 , 8 t val (ptp) clk to signal valid delay ? point-to-point signals 26ns 1 , 2 , 3 , 8 t on float to active delay 2 ns 1 , 8 , 9 t off active to float delay 14 ns 1 , 9 t su input setup time to clk ? bused signals 3ns 3 , 4 , 10 t su (ptp) input setup time to clk ? point-to-point signals 5ns 3 , 4 t h input hold time from clk 0 ns 4 t rst reset active time after power stable 1ms 5 t rst-clk reset active time after clk stable 100 s 5 t rst-off reset active to output float delay 40 ns 5 , 6 t rrsu pci_req64# to pci_rst# setup time 10t cyc ns t rrh pci_rst# to pci_req64# hold time 050ns t rhfa pci_rst# high to first configuration access 2 25 clocks t rhff pci_rst# high to first pci_frame# assertion 5clocks t ckskew clock skew between any pci_clko[3:0] outputs 130 ps notes: 1. refer to the timing measurement conditions in the pci r3.0, figure 7-3. it is important that all driv en signal transitions drive to their v oh or v ol level within one t cyc . 2. minimum times are measured at the package ball wi th the load circuit illustrated in the pci r3.0, figure 7-7. maximum times are measured with the load circuit ill ustrated in the pci r3.0, figures 7-5 and 7-6. 3. pci_gnt# and pci_req# are point-to-point signals and have differ ent input setup times than bused signals. the setup for pci_gnt# and pci_req# at 66 mh z is 5 ns. all othe r signals are bused. 4. refer to the timing measurement condi tions in the pci r3.0, figure 7-4. 5. when pci_m66en is asserted, clk is stable when it meets the requirements in the pci r3.0, section 7.6.4.1. pci_rst# is asserted and de-asserted asynchronously with respect to clk. (refer to the pci r3.0, secti on 4.3.2, for further details.) 6. float all output drivers when pci_rst# is active. (refer to the pci r3.0, section 4.3.2, for further details.) 8. when pci_m66en is asserted, the minimum specification for t val (min), t val (ptp)(min), and t on can be reduced to 1 ns if a mechanism is provided to guarantee a minimu m value of 2 ns when pci_m66en is de-asserted. 9. for purposes of active/fl oat timing measurements, th e hi-z or ?off? state is defined as when the total current delivered through the component ball is less than or equa l to the leakage current specification. 10. setup time applies when the pex 8114 is not driving the ball. devices cannot concurrently drive and receiv e signals. (refer to the pci r3.0, section 3. 10, item 9, for further details.)
january, 2007 serdes interface ac specifications expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 337 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 table 16-10. pci-x 133-mhz ac specifications symbol parameter test conditions min typ max units notes t cyc pci clk cycle time 7.5 30 ns t val clk to signal valid delay ? bused signals 0.7 3.8 ns 1 , 2 , 3 , 10 , 11 t val (ptp) clk to signal valid delay ? point-to-point signals 0.7 3.8 ns 1 , 2 , 3 , 10 , 11 t on float to active delay 0 ns 1 , 7 , 10 , 11 t off active to float delay 7 ns 1 , 7 , 11 t su input setup time to clk ? bused signals 1.2 ns 3 , 4 , 8 t su (ptp) input setup time to clk ? point-to-point signals 1.2 ns 3 , 4 t h input hold time from clk 0.5 ns 4 t rst reset active time after power stable 1ms 5 t rst-clk reset active time after clk stable 100 s 5 t rst-off reset active to output float delay 40 ns 5 , 6 t rrsu pci_req64# to pci_rst# setup time 10 clocks t rrh pci_rst# to pci_req64# hold time 050ns 9 t rhfa pci_rst# high to first configuration access 2 26 clocks t rhff pci_rst# high to first pci_frame# assertion 5clocks t pvrh power valid to pci_rst# high 100 ms t prsu pci-x initialization pattern to pci_rst# setup time 10 clocks t prh pci_rst# to pci-x initialization pattern hold time 050ns 9
electrical specifications plx technology, inc. 338 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 t rlcx delay from pci_rst# low to clk frequency change 0ns t ckskew clock skew between any pci_clko[3:0] outputs 130 ps notes: 1. refer to the timing measurement condi tions in the pci-x r1.0b, figure 9-6. 2. minimum times are me asured at the package ball (not the test point) with the load circuit illustrated in the pci-x r1.0b, figure 9-10. maximum times are measured with the test point and load circuit illust rated in the pci-x r1.0b, figures 9-8 and 9-9. 3. setup time for point-to- point signals applies only to pci_gnt# and pci_req# . all other signals are bused. 4. refer to the timing measurement condi tions in the pci-x r1.0b, figure 9-7. 5. pci_rst# is asserted and de-asserted asyn chronously with respect to clk. 6. float all output drivers wh en pci_rst# is active. 7. for purposes of active/fl oat timing measurements, th e hi-z or ?off? state is defined as when the total current delivered through the component ball is less than or equa l to the leakage current specification. 8. setup time applies only when the pex 8114 is not driving the ball. devices cannot concurrently driv e and receive signals. 9. maximum value is also limited by delay to the first transaction (t rhff ). the pci-x initialization pattern controls signals and pci_req64# after the rising edge of pci_rst# must be de-asserted no later than two clocks before the first pci_frame# and float no later than one clock be fore pci_frame# is asserted. 10. a pci-x device is permitted the minimum values shown for t val , t val (ptp), and t on only in pci-x mode. in conventional pci mode, the device must meet the requirements specified in the pci r3.0 for the appropriate clock frequency. 11. the pex 8114 must meet this specification, indepe ndent of the amount of output s switched simultaneously. table 16-10. pci-x 133-mhz ac specifications (cont.) symbol parameter test conditions min typ max units notes
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 339 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 chapter 17 mechanical specifications 17.1 pex 8114 package specifications the pex 8114 is offered in a 256-ball, 17-mm square plastic ball grid array (bga) package. table 17-1 defines the package specifications. 17.2 thermal characteristics table 17-1. pex 8114 256-ball pbga package specifications parameter specification package type plastic ball grid array package dimensions 17 x 17 mm (approximately 1.86 mm high) ball matrix pattern 16 x 16 mm ball pitch 1.00 mm ball diameter 0.50 0.10 mm ball spacing 0.40 mm table 17-2. pex 8114 package thermal resistance airflow , a. relevant for packages used with external heat sinks. theta 0 m/s 1 m/s 2 m/s c/w ( b. relevant for packages used without external heat sinks. c. the pex 8114 does not require a heat sink during standard operating conditions. 17.8 15.9 14.8
mechanical specifications plx technology, inc. 340 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 17.3 mechanical dimensions figure 17-1. pex 8114 mechanical dimensions
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 341 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 appendix a serial eeprom map for serial eeprom addresses without corres ponding register callo ut (indicated as reserved ), those register locations must be padded with zeros (0000h) when loading the serial eeprom. the last dword in each serial eeprom map is the crc valu e. the offset for the crc is at 03ech. a.1 serial eeprom map table a-1. serial eeprom map register address register name serial eeprom byte offset 000h product identification 0000h 004h command/status 0004h, 0378h (refer to note) 008h class code and revision id 0008h 00ch miscellaneous control 000ch 010h base address 0 0010h 014h base address 1 0014h 018h bus number 0018h 01ch secondary status, i/o limit, and i/o base 001ch 020h memory base and limit address 0020h 024h prefetchable memory base and limit address 0024h 028h prefetchable memory upper base address[63:32] 0028h 02ch prefetchable memory up per limit address[63:32] 002ch 030h i/o base address[31:16] an d i/o limit address[31:16] 0030h 034h new capability pointer (no serial eeprom write) 0034h 038h expansion rom base address (not supported) 0038h 03ch bridge control and interrupt signal 003ch, 037ch (refer to note) 040h power management capability list, capabilities 0040h 044h power management status and control 0044h, 03b8h, 03bch, 03c0h, 03c4h (refer to note) 048h message signaled interrupt capability list, control 0048h 04ch lower message address[31:0] 004ch 050h upper message address[63:32] 0050h 054h message data 0054h 058h pci-x capability list, secondary status 0058h 05ch pci-x bridge status 005ch 060h upstream split transaction control 0060h 064h downstream split transaction control 0064h 068h pci express capability list, capabilities 0068h 06ch device capabilities 006ch, 03a4h (refer to note) 070h device status and control 0070h, 03a8h (refer to note) 074h link capabilities 0074h 078h link status and control 0078h, 03ach (refer to note) 07ch slot capabilities (reverse transparent bridge mode only) 007ch 080h slot status and control (reverse transparent bridge mode only) 0080h 084h - 0fch register addresses skipped
serial eeprom map plx technology, inc. 342 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 100h device serial number extended capability 0084h 104h serial number (low) 0088h 108h serial number (high) 008ch 10ch reserved 0090h 110h reserved 0094h 114h reserved 0098h 118h reserved 009ch 11ch reserved 00a0h 120h reserved 00a4h 124h reserved 00a8h 128h reserved 00ach 12ch reserved 00b0h 130h reserved 00b4h 134h reserved 00b8h 138h device power budgeting extended capability 00bch 13ch data select 00c0h, 03cch, 03d0h, 03d4h, 03d8h, 03dch, 03e0h, 03e4h, 03e8h (refer to note) 140h power data 00c4h 144h power budget capability 00c8h 148h virtual channel budgeting extended capability 00cch 14ch port vc capability 1 00d0h 150h port vc capability 2 (not supported) 00d4h 154h port vc status and control (not supported) 00d8h, 03c8h (refer to note) 158h vc0 resource capability (not supported) 00dch 15ch vc0 resource control 00e0h 160h vc0 resource status 00e4h 164h - 1c4h register addresses skipped 1c8h ecc check disable 00e8h 1cch device-specific error 32-bit error status (factory test only) 00ech 1d0h device-specific error 32-bit error mask (factory test only) 00f0h 1d4h reserved 00f4h 1d8h reserved 00f8h 1dch reserved 00fch 1e0h power management hot plug user configuration 0100h 1e4h egress control and status 0104h 1e8h bad tlp count 0108h 1ech bad dllp count 010ch 1f0h tlp payload length count 0110h 1f4h reserved 0114h 1f8h ack transmission latency limit 0118h 1fch reserved 011ch 200h reserved 0120h 204h reserved 0124h table a-1. serial eeprom map (cont.) register address register name serial eeprom byte offset
january, 2007 serial eeprom map expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 343 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 208h reserved 0128h 20ch reserved 012ch 210h test pattern_0 0130h 214h test pattern_1 0134h 218h test pattern_2 0138h 21ch test pattern_3 013ch 220h physical layer status and control 0140h 224h port configuration 0144h 228h physical layer test 0148h 22ch physical layer (factory test only) 014ch 230h physical layer port command 0150h 234h skip ordered-set interval 0154h 238h quad serdes[0-3] diagnostics data 0158h 23ch reserved 015ch 240h reserved 0160h 244h reserved 0164h 248h serdes nominal drive current select 0168h 24ch serdes drive current level_1 016ch 250h reserved 0170h 254h serdes drive equalization level select_1 0174h 258h - 25ch register addresses skipped 260h serial eeprom status and control 0178h 264h - 2e4h register addresses skipped 2e8h bus number cam 8 017ch, 0388h (refer to note) 2ech reserved 0180h 2f0h reserved 0184h 2f4h reserved 0188h 2f8h reserved 018ch 2fch reserved 0190h 300h reserved 0194h 304h reserved 0198h 308h reserved 019ch 30ch reserved 01a0h 310h reserved 01a4h 314h reserved 01a8h 318h i/o cam_8 01ach, 038ch (refer to note) 31ch - 3c4h register addresses skipped 3c8h amcam_8 memory limit and base 01b0h, 0390h (refer to note) 3cch amcam_8 prefetchable memo ry limit and base[31:0] 01b4h, 0394h (refer to note) 3d0h amcam_8 prefetchable memory base[63:32] 01b8h, 0398h (refer to note) 3d4h amcam_8 prefetchable memory limit[63:32] 01bch, 039ch (refer to note) 3d8h - 544h register addresses skipped 548h reserved 01c0h table a-1. serial eeprom map (cont.) register address register name serial eeprom byte offset
serial eeprom map plx technology, inc. 344 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 54ch - 65ch register addresses skipped 660h tic control 01c4h 664h reserved 01c8h 668h tic port enable (factory test only) 01cch 66ch reserved 01d0h 670h reserved 01d4h 674h reserved 01d8h 678h reserved 01dch 67ch reserved 01e0h 680h reserved 01e4h 684h reserved 01e8h 688h reserved 01ech 68ch reserved 01f0h 690h reserved 01f4h 694h reserved 01f8h 698h reserved 01fch 69ch reserved 0200h 6a0h i/ocam_8 base and limit upper 16 bits 0204h, 03a0h (refer to note) 6a4h reserved 0208h 6a8h reserved 020ch 6ach reserved 0210h 6b0h reserved 0214h 6b4h reserved 0218h 6b8h reserved 021ch 6bch reserved 0220h 6c0h reserved 0224h 6c4h reserved 0228h 6c8h reserved 022ch 6cch reserved 0230h 6d0h reserved 0234h 6d4h reserved 0238h 6d8h reserved 023ch 6dch reserved 0240h 6e0h reserved 0244h 6e4h reserved 0248h 6e8h reserved 024ch 6ech reserved 0250h 6f0h reserved 0254h 6f4h reserved 0258h 6f8h reserved 025ch 6fch reserved 0260h 700h bar0_8 0264h, 0380h (refer to note) 704h bar1_8 0268h, 0384h (refer to note) table a-1. serial eeprom map (cont.) register address register name serial eeprom byte offset
january, 2007 serial eeprom map expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 345 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 708h - 9f0h register addresses skipped 9f4h inch fc update pending timer 026ch 9f8h reserved 0270h 9fch inch mode 0274h a00h inch threshold vc0 posted 0278h a04h inch threshold vc0 non-posted 027ch a08h inch threshold vc0 completion 0280h, 03b0h (refer to note) a0ch - b7ch register addresses skipped b80h reserved 0284h b84h reserved 0288h b88h reserved 028ch b8ch reserved 0290h b90h reserved 0294h b94h reserved 0298h b98h reserved 029ch b9ch reserved 02a0h ba0h - be8h register addresses skipped bech reserved 02a4h bf0h reserved 02a8h bf4h reserved 02ach bf8h reserved 02b0h bfch reserved 02b4h c00h pci express interface pci express itch vc&t threshold_1 02b8h c04h pci express interface itch vc&t threshold_2 02bch c08h reserved 02c0h c0ch reserved 02c4h c10h reserved 02c8h c14h - f50h register addresses skipped f54h reserved 02cch f58h reserved 02d0h f5ch reserved 02d4h f60h reserved 02d8h f64h reserved 02dch f68h reserved 02e0h f6ch reserved 02e4h f70h pci-x interface itch vc&t threshold_1 02e8h f74h pci-x interface itch vc&t threshold_2 02ech f78h reserved 02f0h f7ch reserved 02f4h f80h pci-x interface device-specific error 32-bit error status (factory test only) 02f8h f84h pci-x interface device-specific error 32-bit error mask (factory test only) 02fch f8ch pci-x interface completion buffer timeout 0300h table a-1. serial eeprom map (cont.) register address register name serial eeprom byte offset
serial eeprom map plx technology, inc. 346 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 note: multiple writes to the register are required to trigger the state machine, indicati ng that the serial eeprom is downloaded and to proceed to the next step in the sequence of events. f8ch root control 0304h f90h root status (no serial eeprom write) 0308h f94h root error command 030ch f98c root error status 0310h f9ch error identification (no serial eeprom write) 0314h fa0h pci clock enable, strong ordering, read cycle value 0318h fa4h prefetch 031ch fa8h arbiter 0 0320h fach arbiter 1 0324h fb0h arbiter 2 0328h fb4h pci express enhanced capability header 032ch fb8h uncorrectable error status 0330h fbch uncorrectable error mask 0334h fc0h uncorrectable error severity 0338h fc4h correctable error status 033ch fc8h correctable error mask 0340h fcch advanced error capa bilities and control 0344h, 03b4h (refer to note) fd0h header log_0 0348h fd4h header log_1 034ch fd8h header log_2 0350h fdch header log_3 0354h fe0h secondary uncorrectable error status 0358h fe4h secondary uncorrectable error mask 035ch fe8h secondary uncorrectable error severity 0360h fech secondary uncorrectable error pointer (no serial eeprom write) 0364h ff0h secondary header log (no serial eeprom write) 0368h ff4h 036ch ff8h 0370h ffch 0374h na location of serial eeprom check sum 03ech table a-1. serial eeprom map (cont.) register address register name serial eeprom byte offset
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 347 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 appendix b sample c code implementation of crc generator const unsigned long lcrcpoly = 0xdb710641; ///////////////////////////////////////////////////////////////// // function name : fcalclcrc // description : // return type : unsigned long // // argument : unsigned long lfsr // argument : unsigned long plain // unsigned long fcalclcrc( unsigned long lfsr, unsigned long plain ) { int j; for( j=0; j<32; ++j ) lfsr = (lfsr << 1) ^ ( ((lfsr ^ (plain << j)) & (1<<31)) ? lcrcpoly : 0 ); return lfsr; } ///////////////////////////////////////////////////////////////// // function name : calculatecrc // description : // return type : unsigned int // // argument : dword *eeprom // argument : int eepromsize // unsigned long calculatecrc(unsigned long *eeprom, int eepromsize) { unsigned long crcvalue; int ii; crcvalue = crcseed; for (ii = 0; ii < eepromsize-1; ii++) { crcvalue = fcalclcrc(crcvalue, eeprom[ii]); } #ifdef dump_trace dbg_printf("crc value>\t%x.\n",crcvalue); #endif eeprom[eepromsize-1] = crcvalue; return(crcvalue); }
sample c code implementation of crc generator plx technology, inc. 348 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 ///////////////////////////////////////////////////////////////// // function name : checkcrc // description : // return type : unsigned int // // argument : dword *eeprom // argument : int eepromsize // unsigned long checkcrc(unsigned long *eeprom, int eepromsize) { unsigned long crcvalue; int ii; crcvalue = crcseed; for (ii = 0; ii < eepromsize-1; ii++) { crcvalue = fcalclcrc(crcvalue, eeprom[ii]); } #ifdef dump_trace dbg_printf("crc value>\t%x.\n",crcvalue); #endif if(eeprom[eepromsize-1] == crcvalue) return (crcvalue); else return (0); }
expresslane pex 8114bc pci express-to-pci/pci-x bridge data book 349 copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 appendix c general information c.1 product ordering information contact your local plx sales representative for ordering information. table c-1. product ordering information part number description pex8114-bc13bi pex 8114 pci express-to-pci/pci-x bridge plastic bga package (17-mm square, 256-ball) pex8114-bc13bi g pex 8114 pci express-to-pci/pci-x bridge plastic bga package (17-mm square, 256-ball), lead-free rohs green package pex 8114 - bc 13 b i g g ? lead-free, rohs-compliant, fully green i ? industrial temperature b ? plastic ball grid array package bc ? silicon revision 13 ? clock frequency (133 mhz) 8114 ? part number pex ? pci express product family pex 8114rdk-f pex 8114 forward bridge rapid development kit pex 8114rdk-r pex 8114 reverse bridge rapid development kit
general information plx technology, inc. 350 expresslane pex 8114bc pci express-to-pci/pci-x bridge data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 3.0 c.2 united states and international representatives and distributors plx technology, inc., representative s and distributors are listed at www.plxtech.com . c.3 technical support plx technology, inc., technical support information is listed at www.plxtech.com/support/ , or call 800 759-3735 (domestic only) or 408 774-9060.

▲Up To Search▲

Price & Availability of PEX8114-BC13BIG

	To Download PEX8114-BC13BIG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .